VSDSP Forum

There's some register that indicate audio frames drop count or something like that... to verify if VS1053 has discarded some audio frames? No, when there's an error, the next frame header is found and decoding continues. Fortunately Layer II frames are self-contained (layer III uses bit reservoir),...

NB: I decode an MPEG 1 Layer II stream Is the stream guaranteed to be error-free? Are you able to store the data you send to vs1053b? However, I would expect bit errors to cause audio frames to be discarded, and then the finetune value should become negative to play the audio slower to account for ...

Temperature (and voltage) variation affect the oscillation frequency. Capacitance also affects the oscillation frequency - how well protected is your card? Is it in a metal enclosure? The card being a different temperature would explain some long-term variance. During winter the air is quite dry an...

Here another measurement... The system has running for about 20 hours with stabilized SRC and buffer value then the buffer filling increase instantaneously without any apparent reason (I'm monitoring the input stream and it has constant rate). The SRC control algo compensate the buffer filling and t...

We have experienced a problem using your VS1053 with the sample rate fine tuning. We extract a MP2 stream from a live satellite DVB transport stream and send it to the VS1053, and then send de decoded audio (in I2S format) to an FPGA to process the audio. We are using the last (2.9) VS1053 FLAC_LATM...

Hi Pasi, To modify the sample rate I use the fine tuning by using this function available with Patch 2.4 (15/16 resampler is also enabled) void AdjustRate(int32_t ppm2) { VS1053_Write_Reg(SCI_WRAMADDR, 0x1e07); VS1053_Write_Reg(SCI_WRAM, ppm2); VS1053_Write_Reg(SCI_WRAM, ppm2 >> 16); // oldClock4KHz...

Dear support, I'm using the VS1053b with patch 2.4 with FLAC plugin. My application decode an MPEG2 (MPEG1 layer 2) audio streaming coming from satellite. An FPGA extracts the ES from the satellite transport stream and puts in a FIFO. This FIFO is read by an MCU that fills a local buffer. 32 bytes o...

Hi, Thank you for your answer! My next question is: how I can find the right "tuning word" (fine tuning value) to follow the encoder clock and prevent fifo overflows/underlows? The solution is to implement a software PLL that calculate the tuning word based on FIFO filling indication, then I've impl...

I'm trying to receive a MP2 stream from a SPI (serial peripheral interface) and send to the VS1053b (with FLAC patch 2.4). I receive 4 bytes at time and send immediately to the VS1053b if ((fpga_datavailable() == 1) && (vs_request() == 1)) { //Read from SPI FPGA_Read_Audio(localbuf, FPGA_READBUF); /...

If I've understand right, the I2S output is taken before the SRC not affected by the SRC rate changes. On your opinion, how I can guarantee that will not be any buffer under/overrun into decoder? My idea is to slow shift (upper or lower) the 12,288MHz (XTALI) clock to follow the FIFO filling indicat...