VS1163A Audio Output Bug

Designing hardware that uses VLSI Solution's devices as slave codecs such as an external MP3 decoder chip for a host microcontroller.
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emh203
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Posts: 2
Joined: Mon 2014-10-13 19:12

VS1163A Audio Output Bug

Post by emh203 » Mon 2014-10-13 19:21

Hello:

I believe that I have found a serious bug in the VS1163A (VS1063 without MP3 encoding). We had been developing with the VS1063A for awhile now with now issues. In some new PCB builds, we used an VS1163 to save cost. Upon immediate inspection, we notice a severe distortion/noise in the outputwaveform

I have attached a .PDF that is a screenshot of the problem.

The screenshot is of the VS1163 in the sine wave test mode (outputting 44100 / 128 Hz) using the command sequence:

0x53,0xEF,0x6E,0x01,
0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00


It appears that there is some very odd switching behavior in the output. It almost looks like some sort of overflow or sign bit issue.

There issue seems to be in a internal function after all of the audio generation/decoding. I can see the behavior in the test mode, decoding a .wav or .mp3.

We ruled out any circuit problems as we replaced the VS1163 with a VS1063 and had no issues. We did this procedure twice with new devices.

Please let me know ASAP if this is an issue we can fix with a patch or will require a hardware change.

-Eli
Attachments
VS1163 Issue.pdf
O-Scope capture of the signal output issue
(125.65 KiB) Downloaded 611 times

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Henrik
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Joined: Tue 2010-06-22 14:10

Re: VS1163A Audio Output Bug

Post by Henrik » Tue 2014-10-14 10:46

Hello!

I have just verified a VS1163a here and we can not reproduce your issue.

Our procedure was as follows:
- Write 0x0C20 to SCI_MODE (to activate tests)
- Send your file to the SDI bus

No other operations were done to VS1163. We also tested with 4.5X clock with same results:
- Write 0xC000 to SCI_CLOCKF
- Write 0x0C20 to SCI_MODE (to activate tests)
- Send your file to the SDI bus

If you are using a more complex sequence, please describe it, or alternatively try our ultra-simple examples above.

Please check that your CVDD is in the allowed range of 1.7 - 1.85 volts and that it is properly stabilized. Both too low and too high a voltage will cause memory errors. Too high voltages can also permanently damage the CPU and/or memories.

Also check that you haven't accidentally written anything to the SS_SWING bits of register SCI_STATUS. The three bits should all be zeroes. (Although this error should affect VS1063a and VS1163a similarly).

To me it seems very odd that you are getting these issues with VS1163a's and not VS1063a's. They are produced in the same way, and they have the same firmware. They also go through the exactly same automated production test programs. The only real difference between them is a fuse that disallows MP3 encoding on VS1163a.

If you see this kind of systematic behaviour, the only reason I can think of is that some parameter (like stability of CVDD) is marginal, and it just happens to be that this particular batch of VS1163a's happens to trigger on that while this particular batch of VS1063a's doesn't.

Please let us know if this helps you. If you cannot find a solution, and your device is such that you could provide us with samples of both a working and non-working device, we could have a look at them.

Kind regards,
- Henrik
Good signatures never die. They just fade away.

emh203
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Posts: 2
Joined: Mon 2014-10-13 19:12

Re: VS1163A Audio Output Bug

Post by emh203 » Tue 2015-06-02 4:02

Hello Henrik!


Sorry for extremely late response. I did not realize that there was a response. We had been using our stock of the 1063 devices for our initial production run.

We are at a point where we are doing another run of 150 and we have lot of stock of the old part which we want to use.

Here is the Init Sequence before I send the sine test command. It looks it is similar to what you are doing. (Also we have built a bunch of units around 1063 where everything seems to work OK, not to say there isn't a software error here but something maybe on the "edge" as you pointed out).

Code: Select all


#define	VS1063_REG_SCI_MODE			0x0
#define	VS1063_REG_SCI_STATUS		0x1
#define	VS1063_REG_SCI_BASS			0x2
#define	VS1063_REG_SCI_CLOCKF		0x3
#define	VS1063_REG_SCI_DECODE_TIME	0x4
#define	VS1063_REG_SCI_AUDATA		0x5
#define	VS1063_REG_SCI_WRAM			0x6
#define	VS1063_REG_SCI_WRAMADD       0x7
#define	VS1063_REG_SCI_HDAT0		0x8
#define	VS1063_REG_SCI_HDAT1		0x9
#define	VS1063_REG_SCI_AIADDR		0xA
#define	VS1063_REG_SCI_VOL			0xB
#define	VS1063_REG_SCI_AICTRL0		0xC
#define	VS1063_REG_SCI_AICTRL1		0xD
#define	VS1063_REG_SCI_AICTRL2		0xE
#define	VS1063_REG_SCI_AICTRL3		0xF

#define		VS1063_BIT_SCI_MODE_SM_DIFF					(1<<0)
#define		VS1063_BIT_SCI_MODE_SM_LAYER12				(1<<1)
#define		VS1063_BIT_SCI_MODE_SM_RESET				(1<<2)
#define		VS1063_BIT_SCI_MODE_SM_CANCEL				(1<<3)

#define		VS1063_BIT_SCI_MODE_SM_TESTS				(1<<5)

#define		VS1063_BIT_SCI_MODE_SM_DACT					(1<<8)
#define		VS1063_BIT_SCI_MODE_SM_SDIORD				(1<<9)
#define		VS1063_BIT_SCI_MODE_SM_SDISHARE				(1<<10)
#define		VS1063_BIT_SCI_MODE_SM_SDINEW				(1<<11)
#define		VS1063_BIT_SCI_MODE_SM_ENCODE				(1<<12)

#define		VS1063_BIT_SCI_MODE_SM_LINE1				(1<<14)
#define		VS1063_BIT_SCI_MODE_SM_CLK_RANGE			(1<<15)

void InitVS1063()
{
    uint32_t TimeoutTicks = 0;

    XCS_INACTIVE;
    XDCS_INACTIVE;

    //We assume the I/O pins have alread been setup
    Chip_Clock_Enable(CLK_MX_SSP0);


    Chip_SSP_Set_Mode(LPC_SSP0, SSP_MODE_MASTER);
    Chip_SSP_SetFormat(LPC_SSP0, SSP_BITS_8, SSP_FRAMEFORMAT_SPI, SSP_CLOCK_CPHA0_CPOL0);
    Chip_SSP_SetBitRate(LPC_SSP0, 1000000); //The initial Clock rate needs to be lower until he VS1063 clock is boosted
    Chip_SSP_Enable(LPC_SSP0);

#ifdef AUDIO_DMA_ENABLED
    //Enable DMA  Interrupts
    Chip_Clock_Enable(CLK_MX_DMA);

    LPC_GPDMA->CONFIG |= 0x01; //Enable the DMA Controller
    //Make sure DMA functions is enabled in the SSP (page 1053 of the user manual)
    LPC_SSP0->DMACR |= 0x02;
    LPC_GPDMA->INTTCCLEAR = 0x01; //Clear Channel 1 TC Interrupt
    LPC_GPDMA->INTERRCLR = 0x01; //Clear Channel 1 Error Interrupt
    NVIC_EnableIRQ(DMA_IRQn); //Enable DMA IRQs on the NVIC
#endif

    HardResetVS1063();


    //After a hardware reset (or at power-up) DREQ will stay down for around 22000 clock cycles
    while(DREQ_IS_ACTIVE)
    {

        TimeoutTicks++;

        if(TimeoutTicks>1000000)
        {
            break;
        }
    }


    /*Set the VS1063 CLock Frequency*/
    /*Our clock on the PWB is 12.288MHZ.  We will boost by 4   */
    WriteVS1063_SCI_Register(VS1063_REG_SCI_CLOCKF,0xA000); /*after this, we should be at 51.552*/

    while(DREQ_IS_ACTIVE)
    {
        TimeoutTicks++;

        if(TimeoutTicks>1000000)
        {
            break;
        }
    }

    Delay_mS(100); //wait a bit before we try to do any other configuration
    //Make sure system tests are enabled.  We will also enable the Layer I/II decoding
    //We will also make sure that the "new" interface is selected.  This is the default but this will make sure.
    SetBitsVS1063_SCI_Register(VS1063_REG_SCI_MODE,VS1063_BIT_SCI_MODE_SM_LAYER12|VS1063_BIT_SCI_MODE_SM_TESTS|VS1063_BIT_SCI_MODE_SM_SDINEW);


    Chip_SSP_SetBitRate(LPC_SSP0, 8000000);   //Set the SPI clock to something faster now that the VS1063 is at a faster clock

    WriteVS1063_SDI_EndFill(0,2052);

    Audio_UnMute();


}
Let's do this, while I am investigating this issue again on my end, can I ship you a few of our stock?

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Henrik
VLSI Staff
Posts: 1150
Joined: Tue 2010-06-22 14:10

Re: VS1163A Audio Output Bug

Post by Henrik » Tue 2015-06-02 10:32

Hello!

One thing that comes to mind is that you first set the VS1163a clock to 51.552 MHz, then SPI speed to 8 MHz (I think). However, the maximum allowed SPI speed for read/write operations is CLKI/7 = 51.552/7 MHz = 7.36 MHz. Perhaps better test with a slightly lower clock first.

If you still have problems, please have a look at the SCI/SDI signals with a logic analyzer/oscilloscope. If you don't get your problem resolved, please send the images here. If we still can't resolve it, yes, we certainly can have a look at your devices.

Kind regards,
- Henrik
Good signatures never die. They just fade away.

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pasi
VLSI Staff
Posts: 1670
Joined: Thu 2010-07-15 16:04

Re: VS1163A Audio Output Bug

Post by pasi » Tue 2015-06-02 10:47

Have you checked that you don't have any floating pins in the design (especially the xTEST pin). The behavior of those can vary from production lot to the next, and with the amount of static electricity nearby.

Do you still have the failing unit or the failing IC? What's the lot ID and other markings on the chip? Could you send that to us for analysis? Can you heat or cool the IC and see if that changes the behavior.
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