VS1053 GPIO and the SCI

[Panu]

The GPIO capabilities of VS1053 have been extended compared to VS1003 and VS1033. The state of most of the digital pins on VS1053 can now be read through the IDATA registers, and the state of the SO pin can be controlled somewhat by the software.

VS1053 GPIO registers are defined as follows:

IDATA[7:0] bits are connected to the inputs of GPIO[7:0] pins.
IDATA[8] is connected to the input of pin SCLK.
IDATA[9] is connected to the input of pin XCS.
IDATA[10] is connected to the input of pin SI.
IDATA[11] is connected to the input of pin XDCS.

ODATA[7:0] bits are connected to the output register of GPIO[7:0] pins.
DDR[7:0] bits are connected to the output enable controls of GPIO[7:0] pins.

ODATA[8] controls the output state of the SO pin when DDR[8] is set high. There is still a fixed 3-state buffer on the SO pin, which puts the SO pin in high impedance whenever XCS is high. This fixed 3-state buffer cannot be controlled by software.

Note: If you set DDR[8] high, the hardware SCI port controller cannot control the SO pin, so any SCI reads will fail.