Designing hardware that uses VLSI Solution's devices as slave codecs such as an external MP3 decoder chip for a host microcontroller.
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Joined: Tue 2011-09-13 13:29


Post by Tom » Tue 2011-09-13 13:40

Different behaviour between VS1033 and VS1053 / supply sequencing during startup

A VS1053 doesn’t work in an existing VS1033 design with an LPC2366 (new CVDD=1V8), because of high current on CVDD. The reason was the sequencing of CVDD and IOVDD. With an VS1033 there are no Problems if CVDD is earlier then IOVDD.
What can you tell me about the dependencies of the supplies, I couldn't find anything in the datasheets about the supply sequence.
My sample works fine after delaying the CVDD after IOVDD, but how can I estimate the stress for the VS1053 if only CVDD apply ?


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Re: VS1033/VS1053

Post by pasi » Wed 2011-09-14 12:29

Tom wrote:My sample works fine after delaying the CVDD after IOVDD
The level-shifters of the digital IO pads are (by mistake) referenced from CVDD. It is known that if you supply IOVDD without CVDD, a high level on the IO lines will leak power to CVDD. In this case a series resistor on any high-level IO lines will limit the current until CVDD can be supplied.

I don't think the reverse case has ever come up before. (I will talk with the chip guys about the implications.) Usually we recommend keeping the voltages applied and using xRESET for full powerdown mode.
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