Hello VLSI,
In the datasheet of the VS1053, it is explained that the maximum SPI speed for SCI reads is CLKI/7 (see the note at the bottom of page 23 of version 1.31 of the datasheet).
The rationale is that: tWL, tWH, tH each take 2 samples (minimum) and tV requires 25ns.
Therefore tWL + tWH + tH + tV = 6 * CLKI + 25ns, or in practice 7 * CLKI.
However, tH and tWH overlap, and tV and tWL overlap as well.
This would suggest that the calculation must be: max(tH, tWH) + max(tV, TWL) = 4 * CLKI.
Can someone clarify what I am missing?
Regards,
Thiadmer Riemersma
Clarification of maximum SPI speed for SCI reads
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compuphase
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Re: Clarification of maximum SPI speed for SCI reads
When reading, you need to take into account
1.The microcontroller reads data on the rising edge. VS10xx puts data out when it detects a falling edge.
2. CLKI is asynchronous to the SPI clock -> 0..1 CLKI of delay for detecting CLK low
3. Input signals are registerized -> 1 CLKI of delay (maybe more) for detecting CLK low
4. 1 CLK to drive the data bit out.
5. Possible setup time requirement for the controller
6. Clock jitter between the controller and vs10xx requires some margin.
CLKI/7 is what we have found reliable. (Although the explanation in the datasheet may be missing a step. Possibly the asynchronicity between CLK and SCK.)
If you can change the time when the controller clocks in the data bit, you may be able to use a higher SPI clock.
For writes you don't need to take pipeline into account, because all signals get pipelined the same amount.
1.The microcontroller reads data on the rising edge. VS10xx puts data out when it detects a falling edge.
2. CLKI is asynchronous to the SPI clock -> 0..1 CLKI of delay for detecting CLK low
3. Input signals are registerized -> 1 CLKI of delay (maybe more) for detecting CLK low
4. 1 CLK to drive the data bit out.
5. Possible setup time requirement for the controller
6. Clock jitter between the controller and vs10xx requires some margin.
CLKI/7 is what we have found reliable. (Although the explanation in the datasheet may be missing a step. Possibly the asynchronicity between CLK and SCK.)
If you can change the time when the controller clocks in the data bit, you may be able to use a higher SPI clock.
For writes you don't need to take pipeline into account, because all signals get pipelined the same amount.
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Re: Clarification of maximum SPI speed for SCI reads
Hello!
I'll need to have a good look at the SCI Timing Diagram, but I can see your point that the reasoning for maximum speed seems a little bit odd.
However, to make a long story short, when you are reading from SPI, and assuming you use a 50/50 clock, the maximum speed you may use reliably really is CLKI/7. If you try to increase speed past that, you will end up with bit errors. If you exceed the speed only slightly, bit errors may be so few and far between that the bus and you system may appear working almost perfectly. Which of course causes all kinds of weird error situations and instability, so I definitely don't recommend going above the CLKI/7 speed.
Kind regards,
- Henrik
[EDIT: Ah, Pasi wrote an answer at the same time...]
I'll need to have a good look at the SCI Timing Diagram, but I can see your point that the reasoning for maximum speed seems a little bit odd.
However, to make a long story short, when you are reading from SPI, and assuming you use a 50/50 clock, the maximum speed you may use reliably really is CLKI/7. If you try to increase speed past that, you will end up with bit errors. If you exceed the speed only slightly, bit errors may be so few and far between that the bus and you system may appear working almost perfectly. Which of course causes all kinds of weird error situations and instability, so I definitely don't recommend going above the CLKI/7 speed.
Kind regards,
- Henrik
[EDIT: Ah, Pasi wrote an answer at the same time...]
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compuphase
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Re: Clarification of maximum SPI speed for SCI reads
Hello Pasi & Henrik,
Thanks. I hadn't taken asynchronous clocks into account. It is clear now.
Regards,
Thiadmer Riemersma
Thanks. I hadn't taken asynchronous clocks into account. It is clear now.
Regards,
Thiadmer Riemersma