Hi,
VS1063A acting as a slave processor connected to MCU master processor communicating using SPI protocol.
Input: sine wave 5KHz 1Vpp from function generator connected to LINE1 input.
VS1063 configuration: (Master SPI clock = 1MHz, Chip Select = falling edge, MSB = First)
1. SCI_MODE = SM_SDINEW|SM_SDISHARE|SM_RESET
2. Dummy writes to AICTRL1/AICTRL2 register to make sure the device responds coming out of reset
3. CLOCKF = 0xE000 (5.0x MULT, NO Addition)
4. SCI_VOL = 0x0C0C
5. Load the latest (2.5 version) patches
6. Recording parameters
a. RECRATE = 48KHz
b. RECGAIN = 1024
c. RECMODE = RM_63_FORMAT_MP3 | RM_63_ADC_MODE_JOINT_AGC_STEREO
d. RECQUALITY = RQ_MODE_VBR | RQ_MULT_1000 | 192 ==> (translates to 192Kbps)
7. SCI_MODE = enable SM_LINE1 and SM_ENCODE
8. SCI_AIADDR = 0x0050
My software reads the SCI_HDAT1 to determine the number of valid bytes available to read from SCI_HDAT0
Observation:
I always read ZERO value on SCI_HDAT1 register (no encoded data available to read).
Could you please help me troubleshooting my problem ..
Really appreciate all VLSI staffs for their continued support on these discussion forums.
VS1063 MP3 Encoding
Re: VS1063 MP3 Encoding
For 7, you still have SM_SDINEW (and SM_SDISHARE) also set (and SM_RESET clear)?
Does your patch upload work when you play files?
Have you tried to start the encoding mode without the patches? (set SM_ENCODE + SM_RESET instead of writing to AIADDR)
Does your patch upload work when you play files?
Have you tried to start the encoding mode without the patches? (set SM_ENCODE + SM_RESET instead of writing to AIADDR)
Visit https://www.facebook.com/VLSISolution VLSI Solution on Facebook
Re: VS1063 MP3 Encoding
Pasi,
Thank you for the suggestions...
Yes, step #7 both SM_SDINEW & SM_SDISHARE bits are set and SM_RESET bit is cleared.
Scope of my project is to only encode audio data using VS1063A chip thus I haven't tried playing mp3 data using this chip.
I have tried activating ENCODING without the patch (set SM_ENCODE and SM_RESET bit), still I don't see any non-zero value read from SCI_HDAT1 register.
Are there any internal register that can be read to Analog2Digital outputs (to confirm that audio signal does get into ADC peripheral) ?
Thank you for the suggestions...
Yes, step #7 both SM_SDINEW & SM_SDISHARE bits are set and SM_RESET bit is cleared.
Scope of my project is to only encode audio data using VS1063A chip thus I haven't tried playing mp3 data using this chip.
I have tried activating ENCODING without the patch (set SM_ENCODE and SM_RESET bit), still I don't see any non-zero value read from SCI_HDAT1 register.
Are there any internal register that can be read to Analog2Digital outputs (to confirm that audio signal does get into ADC peripheral) ?
Re: VS1063 MP3 Encoding
Back to basics:
- Do you have AVDD?
- Does RCAP raise to 1.2V?
- CVDD is 1.8V?
However, you should be reading non-zero from HDAT1 regardless of analog input.
- Do you have AVDD?
- Does RCAP raise to 1.2V?
- CVDD is 1.8V?
However, you should be reading non-zero from HDAT1 regardless of analog input.
Visit https://www.facebook.com/VLSISolution VLSI Solution on Facebook