Matching to ADC Line-in levels

Discussion about writing software for VS1005 and the VSOS Operating System. Also posts about VS1005-related hardware design and device drivers should be posted here.
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msat
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Posts: 15
Joined: Tue 2019-05-14 16:52

Matching to ADC Line-in levels

Post by msat »

Hello again!

My project will rely heavily on the VS1005 line inputs so I need to make sure my circuit matches the performance of these inputs as much as possible. One of these inputs will be fed by an electret microphone. Right now I am leaning towards the PUI AOM-5024L-HD-R (https://www.puiaudio.com/products/AOM-5024L-HD-R), which at 80dB SNR and a dynamic range of 96dB, is closely matched with the VS1005's ADC. Since it also has a high sensitivity of -24dBV, the output appears to be a little too "hot" for the mic preamps in the 1005 (at least according to the datasheet) at higher SPLs, but too low for the line-in. What I'm thinking of doing is placing a fixed gain amp stage between the mic and the 1005, and then performing the user-adjustable gain in software. Ok, that all seems pretty straight-forward. I guess the question is, what should be my target input level for max dynamic range? 2200mVpp? 2800? 3280 (per "VS1005 APPNOTE: DEVBOARD PERFORMANCE")?

As a side question, why is Vrms sometimes used to specify max input levels rather than Vpp which seems like the actual critical value we need to be worried about?
Hannu
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Posts: 361
Joined: Mon 2016-05-30 11:54

Re: Matching to ADC Line-in levels

Post by Hannu »

Interesting device. Having the first stage amplifier inside the capsule where it shouldn't catch all electrical noise and decreases output impedance.

If you can test with some random speaker and mic amplifier system to catch the faintest sound you should be able to catch and then amplify it until you caught it. Now go to the other end of dynamics and see where the ADC clips or distortion gets too high. Just to get the feel of it and in the ball park.

The thing is that when going 2.2Vpp to 3.2Vpp (0.77 to 1.13 Vrms) the difference is some dB. 0.77 to 1.54 Vrms would be +6 dB and +3dB SPL and your amplifier would be doubled. Also 3.2Vpp is the maximum measurable signal with distortion and 2.2Vpp is within specified distortion. The noise floor would be under 1 mV if I calculated this correctly with typical -90 dB S/N. And with lower signals, you have 98 dB dynamic range so use 32 bit mode.

Most of the time Vrms make nice calculations and peak values come after designing system to tell you how you forgot to leave the sqrt(2)*Vrms headroom. Think about dBV. 1 Vrms@1 kHz is same as 1 Vdc, 0 dBV.

Oh and the last thing... working with -90dB S/N it is easy to layout the board. Just be careful, think return currents and keep design tight. After that things get slow and hard and every possible change has to be prototyped and tested to squeeze just one more dB S/N.
msat
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Posts: 15
Joined: Tue 2019-05-14 16:52

Re: Matching to ADC Line-in levels

Post by msat »

Hannu to the rescue once again! :)

Ok, I think I'm following along, so let me see if I got this right: 3.2Vpp corresponds to 0dBFS. If we stay below 2.2Vpp, that keeps us in the most linear and distortion-free region of the ADC. If I used my calculator right, the difference between those two is about 3.3dB. If the max dynamic range of the 1005 ADC is 98dB, but we want to stay within 2.2Vpp, then 98dB - 3.3dB gives us an effective dynamic range of 94.7dB. Is that correct?

"Most of the time Vrms make nice calculations and peak values come after designing system to tell you how you forgot to leave the sqrt(2)*Vrms headroom. Think about dBV. 1 Vrms@1 kHz is same as 1 Vdc, 0 dBV."

This is so obvious now that you say it! Thanks!

Thanks for the advice regarding board layout. I'll be heading down that road soon, so I'll keep your recommendations in mind while I further research best practices.
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