§C1. All counters are set to zero at reset
§C2. CorePLL runs at 8 x crystal, generating Video Core Clock (VClk, PLLClk).
§C3. Video Core Clock is divided by 8, generating Color Clock (CSClk, Color Subcarrier Clock). Color Clock is crystal frequency multiplied by 8 and divided by 8, e.g. ColorClock runs at the same frequency as the crystal (but not necessarily at the same phase).
§C4. Video Core Clock is divided by PROGRAM_LENGTH (VDCTRL2[13:10]) to get Pixel Clock.
§A1. The VS23S010 has 1 megabit capacity. There are 1,048,576 bits of SRAM in the VS23S010.
§A2. The VS23S010 has 1,048,576 bits of memory. These are stored at Bit addresses [0...1048575]. Internal logic can access the SRAM array bit by bit using internal shift registers. Some internal registers and data structures in VS23S010 use Bit addressing.
§A3. The 1 megabit of SRAM in the VS23S010 can be seen as consisting of 131,072 bytes of 8 bits each. These are stored at Byte addresses [0..131071]. Some internal registers and data structures in VS23S010 use Byte addressing.
§A4. The 1 megabit of SRAM in the VS23S010 can be seen as consisting of 65536 words of 16 bits each. These are stored at Word addresses [0..65535]. Some internal registers and data structures in VS23S010 use Word addressing.
§A5. The 1 megabit of SRAM in the VS23S010 can be seen as consisting of 32768 longwords of 32 bits each. These are stored at Longword addresses [0..32767]. Some internal registers and data structures in VS23S010 use Longword addressing. The SRAM array is physically accessed, read and written as Longwords. Individual byte operations are carried out internally as 32-bit read-modify-write sequences by internal logic circuitry.
§L1. A Video Frame consists of Lines. There are 263 Lines in a noninterlaced NTSC frame.
§L2. Lines start at fixed intervals.
§L3. The length of a Line is LINE_LENGTH number of Video Core Clocks (VClks, PLLClks).
§L4. At the start of a new line, several things happen:
§L4.1 The DAC output (DC value) is set to zero (0, Sync Level).
§L4.2 The CL (Current Line) line counter is incremented.
§L4.3 24 bits are loaded from Byte address [INDEXSTART * 4 + CL * 3] into an internal register P. P[23:4] is LineIndex, which is a Bit address of the memory location containing picture pixel data for that line. P[3:0] is ProtoOffset, which is used to calculate the memory address of the Prototype (Sync+Background pixels) pixel data for that line.
§L4.4 Let there be internal register ProtoIndex, which is used for incrementing a memory pointer for accessing Prototype (Sync+Background) data. If LineIndex points to a location in memory, which is before INDEXSTART, then ProtoIndex is loaded with LineIndex. Otherwise, Protoindex is loaded with [ProtoOffset * 512 * 8].
§L4.5 Internal SRAM memory load from Bit address [ProtoIndex] to internal pixel data shift register is started.
§L5 10 VClk cycles after start of each new line, pixel data has arrived from SRAM array to internal shift register and Pixel Generation begins in Prototype mode.
§L6 In Prototype mode, SRAM data is interpreted as YUV844 data. The 8 Y bits correspond to DAC output values from 0 to 255 (sync level to light gray).
§L7 For each cycle of Color Clock (CSClk, VClk/8), ProtoIndex is incremented by 16 bits. If we're still in Prototype mode, then 16 bits of fetched YUV844 data is transferred to the Video Modulator and new data is fetched from the SRAM array as needed.
§L8 SRAM memory addresses from 0 to Word address [Color Clocks per Line] always contain a prototype line definition. This begins with a bunch of zeroes for the horizontal Sync pulse pixels, followed by Blank pixels, Color Burst pixels, some more Blank pixels and background picture pixels.
§L9 After the first protoline (which is guaranteed to be at memory address zero), any number of additional protolines can and must be defined, mainly because of vertical syncing.
§L10 If PICSTART number of Color Clock cycles have elapsed since the start of line AND LineIndex points to a memory location AFTER INDEXSTART, then the chip switches from Prototype mode into Picture mode.
§L11 When PICEND number of Color Clock cycles have elapsed since the start of line, the chip resumes to or remains in the Prototype mode.
§L12 When the CL (Current Line) line counter reaches the LINECOUNT number of lines, CL is reset to line zero.
§P1 When the chip is in Picture mode, value of 102 decimal is added to the DAC input. This causes 8 bit data input range of (0...255) to correspond to (black...white) instead of (sync...gray).
§P2 A Microcode Engine governs the fetching of bits from a SRAM shift register into the Y, U and V registers of the Video Modulator.
§P3 At each VClk, the Microcode Engine can pick 1 to 8 bits of data from the shift register to Y, U, V or nowhere, and shift 0 to 6 bits out from the shift register.
§P4 The bits picked from the shift register and written to Y, U or V are extended to the length of the Y, U and V registers as defined in the datasheet.
§P5 After PROGRAM_LENGTH steps, the Microcode Engine returns to step 0 and the generation of a new pixel resumes.
§M1 The Video Modulator generates a digital video signal from the Y, U and V registers to the DAC input. The DAC converts it to an analog current output.
§M2 The Video Modulator has two modes, NTSC mode and PAL mode, where the sign of V is altered at the change of each line.
§M3 The Video Modulator runs at the Video Core Clock frequency.
Designing hardware and software that uses the VS23S0X0 family of ICs as a 8-bit or SPI SRAM memory or as a Video Controller for generating Composite Video (TV-Out) or driving other kinds of displays.
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