VS23S010 and VGA monitor

Designing hardware and software that uses the VS23S0X0 family of ICs as a 8-bit or SPI SRAM memory or as a Video Controller for generating Composite Video (TV-Out) or driving other kinds of displays.
wfriedrich
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Posts: 22
Joined: Tue 2017-08-08 13:46

Re: VS23S010 and VGA monitor

Post by wfriedrich » Mon 2019-02-11 18:06

Hannu:
Hannu wrote:
Mon 2019-02-11 8:14
You have had nice progress. If you get HSYNC and VSYNc right, you have half of problem solved. Next is the blank level on the front and back porches.

I hope you have level shifters between VS23S and arduino. VS23S doesn't like 5 volts.
Yes, I have level shifters, schematics can be found at my project description:
https://hackaday.io/project/21097-ntscp ... lay-shield

Panu:
Yes, I am using GP0 as VSYNC and GP1 as HSYNC. I was trying to copy your example as close as possible. Just probing the pins with a scope at the moment. So that seems to be working. Code to follow.

Code: Select all

		// Use GP pins to set HSYNC start
		w = PROTOLINE_WORD_ADDRESS(0);
		SPIWriteWord((u_int16)w, 0x8160, false);		//GP0=1(VSYNC), GP1=0(HSYNC)
		// Use GP pins to set  HSYNC end
		w = PROTOLINE_WORD_ADDRESS(0);
		SPIWriteWord((u_int16)w+HSYNC_WIDTH_XTALCLKS, 0x8360, false);

Code: Select all

		w = PROTOLINE_WORD_ADDRESS(2);
		SPIWriteWord((u_int16)w, 0x8060, false); //VSYNC + HSYNC start, it's important to have a stable HSYNC, at same location in each line
		w = PROTOLINE_WORD_ADDRESS(2)+HSYNC_WIDTH_XTALCLKS;
		SPIWriteWord((u_int16)w, 0x8260,false); //HSYNC end, keep VSYNC at sync
		SPIWriteWord((u_int16)w+1, 0x0090,false);
- Wolfgang.

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Panu
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Re: VS23S010 and VGA monitor

Post by Panu » Tue 2019-02-12 9:50

Ok, hmm, what is your most immediate problem? Wrong number of lines?

BTW, HSYNC width must be in colorclocks since that's the protoline pixel frequency.

-Panu
Info: Line In and Line Out, VS1000 User interface, Overlay howto, Latest VSIDE, MCU Howto, Youtube
Panu-Kristian Poiksalo, VLSI Solution Oy

wfriedrich
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Posts: 22
Joined: Tue 2017-08-08 13:46

Re: VS23S010 and VGA monitor

Post by wfriedrich » Tue 2019-02-12 19:02

The HSYNC width is copied straight from your code vga.c line 193. But it seems to be correct as the scope image show.

Next problem to solve: The alignment von HSYNC to VSYNC and number of lines. I probably won't have time before the weekend (unless I get snowed in at home without power outage tomorrow :lol: ). I will know more when I hook the board up to a display, once the cable is built.
No worries for now. Stay tuned, I will report back.
Cheers, - Wolfgang.

wfriedrich
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Posts: 22
Joined: Tue 2017-08-08 13:46

Re: VS23S010 and VGA monitor

Post by wfriedrich » Mon 2019-02-18 5:28

Panu, Hannu,

I made some progress and have a stable 640x480 @60Hz frame sometimes. Sometimes my monitor does not sync. Not sure why, maybe it's the cable, as my SYNC wires don't have a nice GND. I also could see grey levels when I added some pattern into protoline 0.
But as soon as I try to set pic line indexes to point to protoline 0 and their individual picture line, some HSYNC pulse disappear and the monitor does not sync anymore (understandable). Seems to be a matter of the right memory address, as LINE_WORD_ADDRESS and LINE_ADDR_16 return different values. Still have to fully understand the formulas for both.

Cheers,
- Wolfgang.

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