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Protoline voltage levels

Posted: Thu 2020-07-30 3:04
by wfriedrich
Hello Panu and team,
Is it possible to select more than 3 voltage levels in a protoline during the non-picture period. I understand how to create blank-level, black-level and sync-level. if I add another value, will it just create one more voltage step? E.g. 0x0000 for sync, 0x0037 for blank, 0x0042 for black level. If I use 0x0020, will the out just create another voltage level between sync and black?
Background to this question is an attempt to generate the VSYNC and HSYNC signal for a VGA display from the V0 core in the VS23S040 and have all IOs for a fast 8bit parallel access.

This is my intended circuit:
Circuit.PNG (50.79 KiB) Viewed 1415 times
And a snapshot of an Excel simulation:
sync sim.PNG
sync sim.PNG (49.85 KiB) Viewed 1414 times
The 3 resistor voltage divider + the V0 signal run into 2 LVDS receivers used as comparators to generate a v-sync pulse and the 2 resistor divider to generate the h-sync. With the picked resistor values, I have the following states:
V0 = 0.7V : Vsync =1, Hsync = 1
V0 > 0.8V : Vsync =0, Hsync = 1 // Vsync only pulse
V0 = 0.5V : Vsync =1, Hsync = 0 // Hsync only pulse
V0 < 0.4V : Vsync =0, Hsync = 0 // Vsync pulse during Hsync pulse

I picked the LVDS recievers as comparators for their propagation delay of a few nsec only and the gates for 5Vlevels to the display.

- Wolfgang.

Edit: Correct designators in sim image

Re: Protoline voltage levels

Posted: Fri 2020-08-07 10:26
by Panu

Yes, the protoline luma value (last 8 bits) is a linear output current value from 0mA to about 60% white. It can be set separately for each protoline pixel (8 master clocks or 1 color subcarrier cycle). Please note that VS23S040 has 4 separate dies, so the exact level of each output can be a little different - if you compare them, it's best to have some margin. Also, if the load resistors (75R inside the VGA monitor) are different, then the voltages will also be different. Your schematic doesn't show any load resistors for the video outputs, so the outputs will basically be saturated high to about 3 volts when there is no monitor connected.

Similarly, the voltage level of Video0 will drop about 40% when composite video monitor is connected, because it introduces another 75 ohm load in addition to the one you have on the PCB.

I'm thinking a little that if you want to make it robust AND use voltage level signaling on your PCB, you could have a quad video op-amp on your PCB for driving the outputs and use fixed load resistors on the PCB. To save power and make it more linear, it's a good idea to switch the output to low current mode where the current drive is reduced by about 90%. Looking at the datasheet, it says typical output level in volts to 75 ohm load at white level is 76 millivolts - that's almost exactly 1 millivolt per ohm. So if you want, say, 1 volt for white level, use 1kohm load resistors for each video output. Then you have nice 1 volt voltage level video signals on your PCB and you can use the op-amp to buffer the outputs so the levels don't change when you connect a monitor or TV.


Re: Protoline voltage levels

Posted: Mon 2020-08-10 3:00
by wfriedrich
Hello Panu,
Thanks for the information, as usual super helpful and gives a lot of insights into the chip.
There might be a slight miss-understanding with my schematic. It is basically a dual purpose, I want to use it either as 4x composite video output, R16 and the load resistor R28 and all the comparators will not be populated in this mode.
The other option would be VGA output with HSYNC and VSYNC generated from the Video0 signal to have all IOs free for a 8 bit parallel data interface. J3 will not be usedas video output in this mode. For this mode your idea with a higher value load resistor is very helpful to make the voltage levels more robust.
Video1-3 would always either composite video or drive the RGB values for the VG interface.

I remember to have seen your schematic of the VGA demo,but I cannot find it any more. Could you please send a link to it again.

- Wolfgang.