PCB design and ground layout considerations

Installing and using VSIDE tools for VLSI Solution's devices that contain a VSDSP signal processor.
User avatar
Panu
VLSI Staff
Posts: 2308
Joined: Tue 2010-06-22 13:43

PCB design and ground layout considerations

Postby Panu » Tue 2010-12-21 15:17

Ground layout is one of the trickiest parts of analog design. There's some discussion about the subject at the Simple DSP Board Application Note, at http://www.vlsi.fi/fileadmin/evaluation_boards/vs1053an_simple_dsp.pdf, chapter 1.4, "PCB Layout".

The easiest way to good analog performance often comes with separate analog and digital grounds, while the most robust, reliable and ESD-tolerant design comes with using a single ground plane. These two goals can be achieved at the same time. Read forward to find out how.

Differences on the potentials of different GND pins can cause large ground currents in the chip, which are harmful. So if you want to use different grounds for analog and digital, you need to make all the ground tracks large enough, so that the ground is very strong at all points.

The most important thing to consider for ground layout is that all signals should flow directly over a ground plane, and that they should not cross any gaps in the ground plane. See the following picture, which is an example of bad design, try not to do this:
groundplane2.png
groundplane2.png (25.8 KiB) Viewed 8132 times
The return current of the signal is forced to go around the gap in the plane, so they don't flow directly over each other. This causes the effective ground plane to be much smaller than what it seems. Also the return paths of different frequency components in the signal are different; high frequency return currents tend to flow close to the signal trace (minimum inductance path) and low frequency components take the shortest (minimum resistance) path. The more different the forward and return paths of the current are, the more different are their impedances. The impedance difference causes signal quality problems. The "Area of Problems" is not the source of the problem, but minimizing the area minimizes the problem. Then consider that you have other signals that also cross the gap in the ground plane. It becomes highly difficult to analyze the behaviour of the return currents and how they affect each other.

All VS10xx devices in LQFP package have their analog pins along the top edge of the IC. If you want to keep analog and digital grounds different, below is one suggestion on how to split the ground plane. This is a good design example, always try to do this:
groundplane3.png
groundplane3.png (32.87 KiB) Viewed 8132 times
The plane is not split under the IC, but you should not route any signals over the dashed line, along with the planes combine under the IC (marked "No routing zone" in the picture). This way the plane is uniform under all pins of the IC, but there's minimal coupling between analog and digital signals.

Of course, as a direct consequence of the "don't cross the gap" rule, it's absolutely forbidden to route any digital signals over the analog ground area.

Also a couple of small hints for PCB layout design:
1) The RCAP capacitor should be the first component that you place and route beside the VS10xx chip. You should have no vias between RCAP and the VS10xx.
2) Try to route the analog outputs (LEFT, RIGHT, and especially GBUF) to the connector without using vias.

Comments welcome!

-Panu
Info: Line In and Line Out, VS1000 User interface, Overlay howto, Latest VSIDE, MCU Howto, Youtube
Panu-Kristian Poiksalo, VLSI Solution Oy

User avatar
Panu
VLSI Staff
Posts: 2308
Joined: Tue 2010-06-22 13:43

Re: PCB design and ground layout considerations

Postby Panu » Fri 2015-04-17 14:15

Design Links:

Tips and Guidelines for Designing VS1005 Boards: viewtopic.php?f=13&t=1500

Please add more.
-Panu
Info: Line In and Line Out, VS1000 User interface, Overlay howto, Latest VSIDE, MCU Howto, Youtube
Panu-Kristian Poiksalo, VLSI Solution Oy


Return to “VSIDE”

Who is online

Users browsing this forum: No registered users