Encoding and patch problem with VS1063

[jarry]

I bought VS1063 Simple DSP Professional Kit.
I was able start SPI communication with STM32F4 microcontroller. Saving and loading data is working.
I have two problems:

1) I can’t load the patch. VS1063 stop responding after loading about 300 to 400 words of data. DREQ signal usually goes into and stays low. The system stops responding.
I enclose oscilloscope graph below.



The markings on the chart:
D0 - SCK
D1 - XCS
D2 – SO
D3 – SI
D4 - DREQ
Clock phase: The second clock transition is the first data capture edge.
Record has been tested with different clock frequencies. The result was always the same.
What could be wrong?

2) Which must be the setting for the G.711 and G.722 coding?
I ran the PCM encoder for encoding. It works well.
Using for example G.711coding VS1063 can not keep up. VS1063 encodes about 2 seconds then stops and resumes encoding. As a result, the sound is unreadable.
I enclose the initialisation code for the microcontroller STM32F4:

#define KODER_DEKODER_VS1063_CLOCKF 0x03
#define KODER_DEKODER_VS1063_AICTRL0 0x0C
#define KODER_DEKODER_VS1063_AICTRL1 0x0D
#define KODER_DEKODER_VS1063_AICTRL2 0x0E
#define KODER_DEKODER_VS1063_AICTRL3 0x0F

#define KODER_DEKODER_VS1063_SM_LINE1 0x4000
#define KODER_DEKODER_VS1063_SM_RESET 0x0004
#define KODER_DEKODER_VS1063_SM_ENCODE 0x1000

SPI_VS1063_WriteData(KODER_DEKODER_VS1063_CLOCKF, 0x8BE8);
if (error_SPI == 1 || error_VS1063_BUSY == 1)
return;

SPI_VS1063_WriteData(KODER_DEKODER_VS1063_AICTRL0, 8000U);
if (error_SPI == 1 || error_VS1063_BUSY == 1)
return;
SPI_VS1063_WriteData(KODER_DEKODER_VS1063_AICTRL1, 1024U);
if (error_SPI == 1 || error_VS1063_BUSY == 1)
return;
SPI_VS1063_WriteData(KODER_DEKODER_VS1063_AICTRL3, 0x32); //0x22 G.711 mikro-law, 0x42 G.722 . 0xA PCM
if (error_SPI == 1 || error_VS1063_BUSY == 1)
return;
dane = SPI_VS1063_ReadData(KODER_DEKODER_VS1063_MODE);
if (error_SPI == 1 || error_VS1063_BUSY == 1)
return;
SPI_VS1063_WriteData(KODER_DEKODER_VS1063_MODE, (dane | KODER_DEKODER_VS1063_SM_RESET | KODER_DEKODER_VS1063_SM_ENCODE) & ~KODER_DEKODER_VS1063_SM_LINE1);
if (error_SPI == 1 || error_VS1063_BUSY == 1)
return;

Are all the parameters set correctly?

[pasi]

It is hard to say from the picture, but it looks to me your data changes at the rising edge. Rising edge is used when vs10xx clocks in the data, so you should probably reverse the clock polarity (output data on falling edge, vs10xx clocks it on rising edge).

You can also try to add a small delay after each time you write to SCI_WRAMADDR.

[ottinger]

I experienced somewhat similar problems.

I am using an STM8S105 and VS1063 together with the IAR Kickstarter IDE
Schematic can be found here: http://oggstreamer.wordpress.com/2012/0 ... chematics/

The issue that I am observing is that sometimes when I reset the STM8 (either Coldstart or via the ST-Link) the patch to the VS1063 wont load - the DREQ line gets stuck - this happens from time to time and not always!

I measured the following behaviour by reseting via ST-Link:
OOOOOOFFFFOFOOFOOOOFOOOOOOOOOOOOOOOOOOOOFOOOOOOOOOOOOO

O = OK, Patch loaded
F = Failure, DREQ stays low

To trace this issue I ran my Initialisation Routine endlessly and it proved that this only happens after coldstart/ST-Link Reset. Init-Code looks like this:

Code: Select all

dreq_timeout = 0;

InitSPI(SPI_BAUDRATEPRESCALER_256); //Slow SPI for Initialization

VS1053Reset();

VS1053WriteRegister(VS1053_REG_MODE, VS1053_SM_SDINEW | VS1053_SM_SDISHARE); //Set GPIOs as Output

VS1053WriteWram(VS1053_ADDR_DDR,0xff);

VS1053WriteRegister(VS1053_REG_CLOCKF,VS1053_CLOCK_5); // set to 61,44 Mhz Operation

InitSPI(SPI_BAUDRATEPRESCALER_4); //fast SPI approx 3,68 M/bits (Datasheet allows max. 3,5M/Bits)

VS1053WriteRegister( VS1053_REG_STATUS, VS1053ReadRegister(VS1053_REG_STATUS) | 
VS1063_SS_REFERENCE_SEL ); //1,65 Volt Reference

VS1053WaitDreqTimeout();
//while(!VS1053_CHECK_DREQ);

LoadVS1063Patch(); 

VS1053WriteRegister and VS1053WriteWram assure that DREQ is High before writing something
I also tried with SPI_BAUDRATEPRESCALER_8 - same result
VS1053Reset - produces a Reset Pulse of at least 2ms.

Usually the DREQ-Failure occured when loading the plg-plugin-array at position 916 to 3195. Positions 919, 1408 and 1409 showed up most often.

As a workaround I replaced

Code: Select all

while(!VS1053_CHECK_DREQ);

with

Code: Select all

void VS1053WaitDreqTimeout()
{
unsigned char delay;

delay = freetimer;
while(!VS1053_CHECK_DREQ && ((unsigned char)(freetimer-delay) <= 5));

if ( !((unsigned char)(freetimer-delay) <= 5))
dreq_timeout++;
} 

freetimer runs at 450 Hz - so after 10ms I notice a DREQ-Timeout. If this happens I restart the Init-Routine and the next time the device comes up and the patch loads sucessfully.

Till now I didn't found the root cause of this issue

[pasi]

Note: if GPIO0 is high during reset, vs10xx tries boot from external SPI memory. DREQ is used as MOSI, so it looks like the decoder is ready, while it actually is not.

So, if the board has GPIO0 floating or high, then add an appropriate delay after releasing reset and checking for DREQ.

[ottinger]

On my PCB I am using a 47k Pulldown - so I am not sure if this is the issue.

http://oggstreamer.files.wordpress.com/ ... vs1063.pdf