All IO pins have a protection diode to the corresponding voltage, so if any of the IO pins get voltage from an external device, you will see that voltage minus ~0.6V in IOVDD, maybe less if there is series resistance in the path.
About Power Off:
Certain combinations of residual voltages in IOVDD and CVDD may cause vs1005 to assert the CVDD reset monitor triggering (and possibly the reduced power consumption in reset may cause a bump in the voltages), then releasing, and if the oscillator is still running (e.g. due to residual voltage in IOVDD or IOVDD dropping more slowly) causing a reboot, which then turns on the regulators and the system restarts. I have studied this closely in vs1000. The usual fixes are to have mismatched CVDD and IOVDD capacitors to either a) force CVDD to drop faster (so it stays in reset) or b) force IOVDD to drop faster so that the oscillator doesn't give clock anymore.
ANA_CF1_BTNDIS set to '1' will disable the reset caused by the power button. It doesn't affect the other functions of the power button. You should probably have it set in all vs1005g versions.
SetPower() is a function for the vs1005 developer board power control (SD etc.). It writes to the Power Control Latch using the 8-bit bus and the chip select muxer.
Writing software that controls the system and peripherals such as displays, SD cards, Buttons, LEDs, Serial Ports etc.