Supply Sequence for VS1063A-L

Designing hardware that use VLSI Solution's devices as the system controller for the entire design.
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edensrock
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Supply Sequence for VS1063A-L

Post by edensrock » Thu 2018-10-25 10:35

Dear VLSI Solution team,

I am planning to use VS1063A-L in my application. I would like to ask if there are any requirements with respect to supply sequence? i.e., Does VS1063A-L require any particular order at power-up for AVDD, VDDIO and CVDD?

Thanks.

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pasi
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Re: Supply Sequence for VS1063A-L

Post by pasi » Thu 2018-10-25 10:49

AVDD can be removed or provided at any time. CVDD and IOVDD should go up at the same time as any external circuit driving a high state to the chip, otherwise the current flows through the protection diodes to CVDD and IOVDD. If external circuits are driving 0, then you can remove CVDD and IOVDD.
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edensrock
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Re: Supply Sequence for VS1063A-L

Post by edensrock » Thu 2018-10-25 13:26

Hi Pasi,

Thanks for the quick reply. In our application, the controller will keep all the control line at 0V until the supply rails ramp up completely. However, we are unable to provide CVDD and IOVDD at the same time. As you can see in the attached power schematic, we are basically generating the CVDD from IOVDD using an LDO. The LDO's turn-on time is given as 200us in its datasheet. Will that be a problem?
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pasi
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Re: Supply Sequence for VS1063A-L

Post by pasi » Thu 2018-10-25 14:25

If the IO lines are kept at 0, then there should not be any special susceptibility for latch-up from there and the delay on CVDD should not be an issue.

Coils are often unnecessary and sometimes detrimental.

Remember to draw analog and digital grounds separately but connect them with 0 ohm under the vs10xx.
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