Schematic Review for VS1003 application (power supply & signal tieoffs)

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Berry
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Schematic Review for VS1003 application (power supply & signal tieoffs)

Post by Berry » Sun 2019-06-16 4:48

Hi

Could someone please critique my circuit attached. Please note that I don’t have any audio-in, I’m only using the VS1003 chip as an MP3 decoder chip with a line-out and on PCB speaker. The SPI interface is for talking to a memory IC. More specifically, I’d like feedback on the following (all tie-off and power-supply related):

1. My IOVDD is 3.3V (has to be due to MCU and other system requirements). This is generated by an LDO. My CVDD and AVDD are shorted and generated by second LDO with output of 2.8V. It looks like GND is shared internally to the VLSI chip between AVD and CVDD (?) and if so, will my configuration be a problem? (ie. GND is shared between AVD and CVDD internal to the chip, but external CVDD and AVD are shared externally)

2. In the datasheet, I see a 100nF cap for each power pin, plus 1x 10uF cap for each power supply. Naturally, each 100nF cap should be placed beside each power pin. However, it's not clear what the 10uF cap per rail is for and where is it to be placed. I already have the appropriate caps at the output and input of my LDOs. Is this 10uF cap still required per power supply in my case? My LDO caps are as per LDO manufacture recommendations and are much less than 10uF. (2.2uF at 3.3V LDO input/output, 4.7uF at 2.8 LDO input/output)

3. Please confirm that I tied off unused pins correctly? That is pins 1,2,9,10,33,34,48. Basically, I use a pull-down 100K resistor.

4. For the UART TX & RX pins, I will only use them for debug. They have no use in functional mode. For those, I’ve used a 100k pull-up resistor and have test points for use during debug. For #3 & #4, I’m seeing conflicting recommendations between the forum and datasheet, so would like to confirm.

Thanks!
Berry
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pasi
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Re: Schematic Review for VS1003 application (power supply & signal tieoffs)

Post by pasi » Mon 2019-06-17 10:36

1. The grounds are connected inside the chip, but you should connect analog and digital grounds below the vs1003 to avoid ground currents going through the IC. (I.e. design with separate analog and digital grounds, then connect them with 0-ohm traces below the IC.)

2. 10uF is for "fast" and 100nF for "slow" filtering.

3. I would not connect analog and digital pins to the same pull-down.

4. TX doesn't strictly need a pull-up unless you keep the IC in reset for long periods (TX is an input during reset).

Other: You don't seem to have capacitors to ground on the crystal. The system might work without, depending on the capacitance of the board and the internal capacitance of the crystal, but....
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Berry
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Re: Schematic Review for VS1003 application (power supply & signal tieoffs)

Post by Berry » Mon 2019-06-17 16:59

Thanks for the feedback, to follow up

1. Got it

2. So I guess the 10uF are still required in addition to the LDO caps. Where should the 10uF be placed, any recommendations? I understand 1x 100nF caps should be placed each power pin, but where to place the 1x 10uF cap of each rail, beside any particular pin?

3. Fixed

4. Initially, I didn't have a pull up, but looking at viewtopic.php?f=9&t=2166&p=11421&hilit=xCS#p11421, Panu's states that pulling up TX high is very important:

"TX: High (surprisingly important)"
"Missing those marked as "Important!" will cause the chip to malfunction in some circumstances"

That was for VS1053 but I assume the same applies to VS1003. Kindly confirm which recommendation is correct.

There's also conflicting information in the VS1003 datasheet, as it states there: "If UART is not used, RX should be connected to IOVDD and TX be unconnected." Best to update to the correct recommendation.


5. Regarding the cap of the xtal, thanks for noting. The xtal we're using is CSTNE12M2GH5L000R0 https://www.murata.com/products/product ... L000R0.pdf from Murata and has 2x 33pF cap built-in (max, +/- 20%, @ 1 Mhz). Are any additional caps still required?


Updated schematic with #1 & #2 fixed attached.

Thanks
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audioIC.pdf
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Hannu
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Re: Schematic Review for VS1003 application (power supply & signal tieoffs)

Post by Hannu » Tue 2019-06-18 10:01

Berry wrote:
Mon 2019-06-17 16:59
Thanks for the feedback, to follow up
2. So I guess the 10uF are still required in addition to the LDO caps. Where should the 10uF be placed, any recommendations? I understand 1x 100nF caps should be placed each power pin, but where to place the 1x 10uF cap of each rail, beside any particular pin?
I spent some time and laid out highly artistic representation capacitors of VS1003
illustration_schem.png
illustration_schem.png (16.19 KiB) Viewed 670 times
The bigger caps are there to filter out noises and provide some separation between analog and digital powers.

On the board side, the ground is separated, but still same. And when bringing the power to VS1003, try to keep the current loop small. I didn't as I wanted to make more readable layout.
illustration_board.png
illustration_board.png (11.62 KiB) Viewed 670 times

5. Regarding the cap of the xtal, thanks for noting. The xtal we're using is CSTNE12M2GH5L000R0 https://www.murata.com/products/product ... L000R0.pdf from Murata and has 2x 33pF cap built-in (max, +/- 20%, @ 1 Mhz). Are any additional caps still required?
Ceramic resonator... You may want to reserve footprint for real crystal. Even the cheapest crystal is better frequency performance. Please let us know if you got ceramic resonator to work as we haven't ever tested that. Is there any particular reason to use 12MHz instead of 12.288 MHz?

Berry
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Re: Schematic Review for VS1003 application (power supply & signal tieoffs)

Post by Berry » Mon 2019-06-24 12:22

Hi ,

Sorry for the delay, as I’m currently out of town and on travel until next week.

2. Regarding the placement of the caps, yes, I saw a similar schematic in the datasheet. However, looking at the PCB footprint, all the power pins are spread across all edges of the chip, even for the same rail. So while the schematic shows them all connected together nicely, in the physical world, it cannot be like that, hence my question, as those pins are not all right beside each other. For example for CVDD, the pins are spread across 3 edges of the IC. Obviously, each of the 3x 100nF caps will be placed beside a CVDD pin, so one per edge. The question is where to place the 4th bigger cap, the 10uF one, in the physical world? I’m wondering if there’s any recommendation or do I just place it beside any CVDD pin randomly?

4. I guess I’ll just follow Panu’s recommendation and keep pull up resistors on both TX and RX UART lines

5. Thanks for the feedback. I choose to use a resonator as opposed to a crystal despite its shortcomings based on VLSI Solutions recommendation after reading these 2 articles which says resonators are more than good enough for this application:

http://www.vlsi.fi/fileadmin/app_notes/ ... onator.pdf
http://www.vlsi.fi/fileadmin/app_notes/ ... _rev07.pdf

In the first article, it states:

“A ceramic resonator is a robust and inexpensive way to provide clock to VS10XX
applications. Compared to a quartz crystal, a resonator can tolerate relatively
hard physical abuse. Ceramic resonators are small and inexpensive but are not as
accurate as quartz crystal. In VS10XX applications the accuracy of a resonator is
usually more than good enough”

Based on that, I assumed resonators have been used and tested to work with VS1003 by VLSI Solutions. Hannu, do you work for VLSI Solutions? When you say “we”, do you mean at “VLSI Solutions” or at your own company? If not, Panu/Pasi, can you please comment on the subject of crystal vs resonator? I’m a little confused now. Have resonators been used and tested to work well with VS1003 at stated in VSLI Solutions app notes and docs?

As for the frequency, “CSTNE12M2GH5L000R0” is actually 12.288 Mhz not 12 MHz. The component number is correct but the link to the datasheet I provided earlier was incorrect. I got that from Digikey as they incorrectly linked it to the 12.288 MHz component and I blindly copied and pasted. I apologize for the confusion. Here’s the correct link to CSTNE12M2GH5L000R0, which shows that its's indeed a 12.288 Mhz component:

https://www.murata.com/en-us/products/p ... 9743213000

Any feedback on this component would be appreciated.

Thanks!

Hannu
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Re: Schematic Review for VS1003 application (power supply & signal tieoffs)

Post by Hannu » Tue 2019-06-25 15:37

Berry wrote:
Mon 2019-06-24 12:22
Hi ,

Sorry for the delay, as I’m currently out of town and on travel until next week.

2. Regarding the placement of the caps, yes, I saw a similar schematic in the datasheet. However, looking at the PCB footprint, all the power pins are spread across all edges of the chip, even for the same rail. So while the schematic shows them all connected together nicely, in the physical world, it cannot be like that, hence my question, as those pins are not all right beside each other. For example for CVDD, the pins are spread across 3 edges of the IC. Obviously, each of the 3x 100nF caps will be placed beside a CVDD pin, so one per edge. The question is where to place the 4th bigger cap, the 10uF one, in the physical world? I’m wondering if there’s any recommendation or do I just place it beside any CVDD pin randomly?
The pins are all around the chip for good and stable powering. When one side of chip requires current, it can get it from capacitor near power pin and power supply charges the capacitor. This usually happens on the clock edge and the peak amperage can be quite high.

Same idea can be applied to the big capacitor. Placing it such way that it is available for current spikes. In my illustration board design, I placed the larger capacitor to trunk of power nets so it is really parallel with all power caps.
4. I guess I’ll just follow Panu’s recommendation and keep pull up resistors on both TX and RX UART lines
It is good advice and shouldn't break the power budget.
5. Thanks for the feedback. I choose to use a resonator as opposed to a crystal despite its shortcomings based on VLSI Solutions recommendation after reading these 2 articles which says resonators are more than good enough for this application:

http://www.vlsi.fi/fileadmin/app_notes/ ... onator.pdf
http://www.vlsi.fi/fileadmin/app_notes/ ... _rev07.pdf

In the first article, it states:

“A ceramic resonator is a robust and inexpensive way to provide clock to VS10XX
applications. Compared to a quartz crystal, a resonator can tolerate relatively
hard physical abuse. Ceramic resonators are small and inexpensive but are not as
accurate as quartz crystal. In VS10XX applications the accuracy of a resonator is
usually more than good enough”

Based on that, I assumed resonators have been used and tested to work with VS1003 by VLSI Solutions. Hannu, do you work for VLSI Solutions? When you say “we”, do you mean at “VLSI Solutions” or at your own company? If not, Panu/Pasi, can you please comment on the subject of crystal vs resonator? I’m a little confused now. Have resonators been used and tested to work well with VS1003 at stated in VSLI Solutions app notes and docs?

As for the frequency, “CSTNE12M2GH5L000R0” is actually 12.288 Mhz not 12 MHz. The component number is correct but the link to the datasheet I provided earlier was incorrect. I got that from Digikey as they incorrectly linked it to the 12.288 MHz component and I blindly copied and pasted. I apologize for the confusion. Here’s the correct link to CSTNE12M2GH5L000R0, which shows that its's indeed a 12.288 Mhz component:

https://www.murata.com/en-us/products/p ... 9743213000

Any feedback on this component would be appreciated.

Thanks!
Yes, I work for VLSI Solution. I have tried to read application notes and lot of other material. I haven't dig that deep to the pile of documents. Those are over ten years old documents and memory of experiments fades. That's why it has been written and published. It is nice to see that the application notes have helped someone.

I don't have personal experience resonators on VLSI Solution chips but last time I tried to use resonators I failed. After that I've liked crystals and oscillators. Anyway. I didn't notice anything which is horribly wrong and the 30 pF load capacitance can be handled be the crystal amplifier.

Berry
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Re: Schematic Review for VS1003 application (power supply & signal tieoffs)

Post by Berry » Sun 2019-06-30 23:33

Thanks for your feedback Hannu. I wasn't aware you work for VLSI Solutions, I thought you're just a power user since your profile doesn't say "VLSI Staff" like it does for Panu and Pasi. Your feedback is always helpful!

In that case, I'll take up your suggestion and add a footprint for a xtal just in case. Will use "XC2786TR-ND" (12.288 Mhz, 18pF) with 33pF load caps.

I was trying to find the exact xtal used by VLSI Solutions dev boards but wasn't able to find it. Can you provide the part number for a xtal used with VS1003?

Regards,
Berry

Hannu
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Re: Schematic Review for VS1003 application (power supply & signal tieoffs)

Post by Hannu » Mon 2019-07-08 8:28

Hi Berry!

We haven't done any new VS1003 design in last few years and couldn't find fresh and good BOM to check this out.

VS1103 is close relative to VS1003 and the VS1103 module VSMD301 http://www.vlsi.fi/fileadmin/modules/vs ... 04_sch.pdf has quite close to your capacitor and it uses 22p capacitors. Anyway your crystal looks good. Depending your layout, you might want to tune the load capacitance.

I did little bit tracking to find out what crystals we have used. In our lab we have:
https://www.digikey.com/products/en?x=1 ... 87-1239-ND
https://www.digikey.com/products/en?x=1 ... -1222-1-ND

I've found those to be easy to solder. Hope this helps in your design.

Berry
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Re: Schematic Review for VS1003 application (power supply & signal tieoffs)

Post by Berry » Tue 2019-07-09 0:41

Hi Hannu

That's perfect. Thanks for all your help!

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