VS1005G-F-Q xreset remains at 0.5V

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DavidMc
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VS1005G-F-Q xreset remains at 0.5V

Post by DavidMc » Tue 2018-12-11 4:42

Hello!

I just received a small proto run of boards and am attempting to boot.

Unfortunately, I cannot find the cause of XRESET pin remaining at 0.5V. :|

The design is stable, so this issue is a bit of a surprise. The major change is that we transitioned the RAM from 1Mb to 4Mb to improve SD card compatibility.

Observations:
- XRESET pin static (DC) impedance to ground and IOVDD is same as known-good PCB. Pull-up resistor measures 100kΩ.
- 12.288MHz is not starting. Swapped all 12.288 components. Caps are 10pF, and parallel 1MΩ is present.
- XTALI and XTALO pins have an extremely brief pulse at boot or turn off, but never oscillation with 10pF oscope probe. Same 10x oscope probe sees 12.288MHz on known-good (prior version) board.
- 32kHz clock is oscillating
- IOVDD is 2.0V
- CVDD is 1.8V
- AVDD is 2.5V
- I've checked the many gpio pins that configure boot.
- D7 is pulled-high (we want 3V3)
- pwrbtn is high
- Vhigh is 5V

some references to somewhat related boot issues:
Pasi said for VS1000:
viewtopic.php?f=8&t=588&p=2291&sid=ab116dc04ecabbefa5175253f707bc97#p2295
GPIO0_7 state is read immediately after the oscillator has started after power-on reset
Not sure if this applies to VS1005G

Also,
Panu said:
viewtopic.php?f=13&t=1485&p=9990&sid=ab116dc04ecabbefa5175253f707bc97#p9990
it needs proper clock and voltages to resume from reset
Any ideas would be greatly appreciated! :)

Thanks!
David McRell

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Panu
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Re: VS1005G-F-Q xreset remains at 0.5V

Post by Panu » Wed 2018-12-12 8:37

Hmm, seems strange... but these things have a tendency to always seem strange until the problem is found.

Right now I'd keep looking at the XRESET pin. That's an input to the whole other bloc of clocking the chip etc. VS1005 power-up goes something like this (recalled from memory so may not be exact):

1. VHIGH is applied -> Stable.
2. PWRBTN is applied -> Power output regulators go to their hardware defaults. PWM relaxation oscillator starts. Otherwise stable.
3. XRESET is brought high in comparison to the decision-making threshold, which in the VS1005G is relative to IOVDD -> XTAL oscillator starts and a hardware delay starts.
4. Hardware delay ends, XTALI is running. After 4 XTALI cycles other parts of the IC will receive synchronous reset. Operation starts.

You say you have received a number of PCBs. Do they all exhibit the same behavior?

Do you have capacitor in the XRESET line? Might it be leaking? Remove the capacitor. Check that it's not actually a diode :lol: which has actually happened.

If you decrease the XRESET pull-up resistance to 10K, does it start then? Is the pull-up towards IOVDD?


Let's check these first and keep in touch!

-Panu
Info: Line In and Line Out, VS1000 User interface, Overlay howto, Latest VSIDE, MCU Howto, Youtube
Panu-Kristian Poiksalo, VLSI Solution Oy

DavidMc
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Re: VS1005G-F-Q xreset remains at 0.5V

Post by DavidMc » Wed 2018-12-12 18:20

seems strange... but these things have a tendency to always seem strange until the problem is found.
Exactly true with this one. :)
If you decrease the XRESET pull-up resistance to 10K, does it start then? Is the pull-up towards IOVDD?
It occurred to me on the way home after posting my forum post, that I had not considered the leakage current of the 4Mb RAM, so the next morning I confirmed that a lower Ω pull-up fixed the problem. The 4Mb RAM has much more leakage current compared to the 1Mb RAM, 8µA vs 2µA. IIRC, I was seeing about 6µA total (VS1005 + RAM), which puts it on the threshold of 0.7*IOVDD logic high given a 100kΩ pull-up.

Yes, I had 2 boards that exhibited the same behavior. No cap on XRESET.

What took me a little time to resolve was a fact that I missed - reset pin logic is evaluated while IOVDD is at its default 2V, not 3V3. I also assumed the 4Mb RAM would have identical specs to 1Mb in this regard, which is my mistake. Details. :)

Panu, thanks for looking in to this. I would have immediately posted my discovery but this was my first post, so I had to wait. :) Perhaps I should have emailed support to let you know you did not need to dig in to this. That said, I do appreciate the boot sequence steps you provided.

Kind Regards,
:David

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