Hello Panu and team,
Is it possible to select more than 3 voltage levels in a protoline during the non-picture period. I understand how to create blank-level, black-level and sync-level. if I add another value, will it just create one more voltage step? E.g. 0x0000 for sync, 0x0037 for blank, 0x0042 for black level. If I use 0x0020, will the out just create another voltage level between sync and black?
Background to this question is an attempt to generate the VSYNC and HSYNC signal for a VGA display from the V0 core in the VS23S040 and have all IOs for a fast 8bit parallel access.
This is my intended circuit:
And a snapshot of an Excel simulation:
The 3 resistor voltage divider + the V0 signal run into 2 LVDS receivers used as comparators to generate a v-sync pulse and the 2 resistor divider to generate the h-sync. With the picked resistor values, I have the following states:
V0 = 0.7V : Vsync =1, Hsync = 1
V0 > 0.8V : Vsync =0, Hsync = 1 // Vsync only pulse
V0 = 0.5V : Vsync =1, Hsync = 0 // Hsync only pulse
V0 < 0.4V : Vsync =0, Hsync = 0 // Vsync pulse during Hsync pulse
I picked the LVDS recievers as comparators for their propagation delay of a few nsec only and the gates for 5Vlevels to the display.
Edit: Correct designators in sim image
Designing hardware and software that uses the VS23S0X0 family of ICs as a 8-bit or SPI SRAM memory or as a Video Controller for generating Composite Video (TV-Out) or driving other kinds of displays.
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