I2S Hardware pull up

Discussion about writing software for VS1005 and the VSOS Operating System. Also posts about VS1005-related hardware design and device drivers should be posted here.
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dalibor2000
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Posts: 7
Joined: Wed 2015-09-02 11:48

I2S Hardware pull up

Post by dalibor2000 » Tue 2018-08-07 17:38

Hi,

Not clear from the datasheet or other documentation for VS1005 what should be the hardware features of the I2S bus.
I have the VS1005 connected to my Class D power amp via I2S, and I am having a lot of EMC trouble with the constant 12.288 MHz clock.
I have 33R in series at the source and a small chip inductor at the sink end, with a 22pF cap to ground. I tried various combinations of components on this line, but I am not able to improve it.

Do you have a reference design for this or any other recommendations? Not sure if this pin needs a pull up either?

Many thanks in advance.
Dalibor

Hannu
Senior User
Posts: 42
Joined: Mon 2016-05-30 11:54

Re: I2S Hardware pull up

Post by Hannu » Wed 2018-08-08 8:57

I2S doesn't need pull-ups unlike I2C.

Does your design require the 12M clock? You can turn it off it isn't needed by flipping one bit with preg in I2S_CF register.

In my limited EMC experience, the I2S and 12M clock should behave nicely. Last time I looked with scope the 12M clock line, it was more like a sine wave than textbook clock. This depends on PCB design.

I would try something like 10R source resistor, 33p sink capacitance. And I would throw the inductors out as usually those just make things harder. The side-effect of the capacitor is that it delays the signal. But that comes from my "Enhanced Magic Circuits for non-initiated" notes.

Just to check...

Did you started with straight wires from VS1005 to amp and measured that? My point being that some amplifier chips amplify digital signals to noise. And if the clock noise isn't changing, it comes from the amp chip.

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