Flashing / Erasing Flash of new or bricked VS1005G board

Discussion about writing software for VS1005 and the VSOS Operating System. Also posts about VS1005-related hardware design and device drivers should be posted here.
Hannu
VLSI Staff
Posts: 561
Joined: Mon 2016-05-30 11:54
Location: Finland
Contact:

Re: Flashing / Erasing Flash of new or bricked VS1005G board

Post by Hannu »

Does the chip get hot?

What are the voltages on left, right and cbuf? What about AVDD?

Shorting left to right isn't as smart as using real amplifier if the gain isn't enough.
Arkantium
User
Posts: 15
Joined: Tue 2022-06-07 16:32

Re: Flashing / Erasing Flash of new or bricked VS1005G board

Post by Arkantium »

Hello Hannu,

Yes, if I apply 5,1 or 5,2 volts The chip is getting about 50ºC (checked with temperature camera) progresively during 30 or 40 seconds, and then restarts.

Yes, I agree that an amplifier is the most optimal solution but I tried this to save space for other ICs (I do not have too much space in this project).

The voltages are:
AVDD-> 3.73V
Right->1.68V
Left->1.68V
Cbuf->1.88V
Hannu
VLSI Staff
Posts: 561
Joined: Mon 2016-05-30 11:54
Location: Finland
Contact:

Re: Flashing / Erasing Flash of new or bricked VS1005G board

Post by Hannu »

Clearly something is taking a lot of power. While you watched the board with thermal camera, were there other interesting hot spots except VS1005?

Was the CBUF voltage really 1.88 or was it a typo?

Todays "I don't know what is happening, but let's try to find out" list:

Are we sure that the power is going out through DAC?
If you comment out auodac line from config.txt, does the chip heat up and reset?

And when the auodac driver is loaded, what does preg -v ANA_CF2 prints? I'm interested ANA_CF2_VCMST bit. If it is high, CBUF is driving heavily.

Does the CVDD drop before reset? because the tens of seconds reset duration is something which would fit CVDD monitor caused reset and if there is some bad short, it could consume power so much that the voltage drops and everything resets.

And have you tried to remove the short between left and right? I'm not sigma-delta expert but I would say that there are high changes that those pin are driving against each other. If you want the +6dB, drive your load from left and right and use ftxmono in differential mode.
Arkantium
User
Posts: 15
Joined: Tue 2022-06-07 16:32

Re: Flashing / Erasing Flash of new or bricked VS1005G board

Post by Arkantium »

Hi Hannu,

No any other component is getting hot except de VS1205GF.

CBUF is around 1.7 and then drops to 1.5 or 1.6 when restarting.

If I comment out AUODAC line form config.txt is still doing the same, heating up and restarting again and again.

When is loaded this is the text:
Driver: Run... preg -v ana_cf2E'preg not found'

CVDD is 1.8V and drops to 1.75V when restarting.

I am trying to chop the track, but it is under de chip and it has been very difficult.

Thanks a lot
Hannu
VLSI Staff
Posts: 561
Joined: Mon 2016-05-30 11:54
Location: Finland
Contact:

Re: Flashing / Erasing Flash of new or bricked VS1005G board

Post by Hannu »

Arkantium wrote: Tue 2023-11-21 13:22
Driver: AUODAC... E'lib'
not loaded
Have you fixed this? You have sys/auodac.dl3 but it is something which doesn't work. Remove and copy from roots and sources package a working version. And run fsck or whatever the filesystem check is called today to have a clean filesystem.
Arkantium
User
Posts: 15
Joined: Tue 2022-06-07 16:32

Re: Flashing / Erasing Flash of new or bricked VS1005G board

Post by Arkantium »

I replaced it for a new auodac.dl3 file from your VSOS_363_RootAndLibrariesSourceCode/SYS_everything and now continue restarting but even before, I mean it starts restarting lines before:

Hello.
VSOS 3.63 build Oct 28 2022 11:57:35
VLSI Solution Oy 2012-2021 - www.vlsi.fi

Starting the kernel..
Starting Devices...
Internal Flash

Installed system devices:
S: 896K SPI Flash c213, handled by FAT.
Load drivers, config 0...
Driver: UARTIN...
Driver: RUN... SetClock 86 -l87 -vSetClock running on VS1205g, clocks:
XTALI 12.288MHz, CLKI 86.016MHz, limit 87.000MHz, src PLL
RAM Delay 1, POR on
CVDD 1.800V(19), IOVDD 3.30V(25), AVDD 3.60V(28)
UART nominal 115200 bps, real 114841 bps (0.3% error), reg 0x006b
SPI0(I) 21.5 Mbit/s, SPI1 43.0 Mbit/s, NAND 43.0 MByte/s, SD 5.4 MByte/s
Uptime 0:00.1, time counter interrupt 1000.0 times/s
Laser fuse(63:0) = 0x2b11:8b81:7156:0408, crc ok
Serial Flash:
RDID: manufacturer c2 (C2), type 20 (20), density 14 (14)
SCUR: 0x00. Factory lock off, user lock off
Field 0, 0x2049 0xb92b 0x9171 0xc000 opCode 1 = TrimData
CRC29: 0x0049b92b, ok
USB Trim: 0x9174
High speed: yes
Mem Delay: 2
Int Flash: 2.8 V
VCORE Trim: +0
Customer code: 0
Unused: 0
Field 1, 0x5801 0x581e 0x001f 0xacef opCode 2 = SerialNumber
CRC29: 0x1801581e, ok
Serial number: 0x001facef
Field 2, 0xffff 0xffff 0xffff 0xffff opCo
Driver: AUODAC... de 7 = Unused
Field 3, 0xffff 0xffff 0xffff 0xffff opCode 7 = Unused
Field 4, 0xffff 0xffff 0xffff 0xffff opCode 7 = Unused
Field 5, 0xffff 0xffff 0xffff 0xffff opCode 7 = Unused
Field 6, 0xffff 0xffff 0xffff 0xffff opCode 7 = Unused

Driver: AUIADC... Input 0x0440 Rat
eDriver: RUN... 48000AuOutput -s4096
Hello.
VSOS 3.63 build Oct 28 2022 11:57:35
VLSI Solution Oy 2012-2021 - www.vlsi.fi

Starting the kernel..
Starting Devices...
Internal Flash


And sorry, but I do not understand what you mean with "fsck", I just initiallised as always, connecting to UART cable.
Post Reply