multiple encoding with vs1063a

Designing hardware that uses VLSI Solution's devices as slave codecs such as an external MP3 decoder chip for a host microcontroller.
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EMBED_LU
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Posts: 6
Joined: Mon 2021-03-15 12:31

multiple encoding with vs1063a

Post by EMBED_LU »

Hello? I'm working on a new study using VS1063 chip. I was grateful for the
previous help.
My current plan is to connect 4 VS1063A to 1 MCU.
Only MOSI and MISO ports will be connected in parallel, CS and DCS will be
used for each VS1063.

Question
1) I want to receive encoded data using UART, not HDAT0,1, then do I need 4
UART?
2) If I receive it as UART, Can I use interrupt or DMA to receive data? I
don't know the mechanism of UART reception.

I'll be looking forward to hearing from you soon. Thank you
Hannu
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Posts: 173
Joined: Mon 2016-05-30 11:54

Re: multiple encoding with vs1063a

Post by Hannu »

EMBED_LU wrote: Wed 2021-04-21 1:51 Hello? I'm working on a new study using VS1063 chip. I was grateful for the
previous help.
My current plan is to connect 4 VS1063A to 1 MCU.
Only MOSI and MISO ports will be connected in parallel, CS and DCS will be
used for each VS1063.
This should be OK. Also SCLK should be shared. If CS lines are high in NEW_MODE, chip shouldn't care what goes on with the bus. A simple way to fail with this is to power off one VS1063 and that would clamp the signals to diode voltage so keep all chips powered or handle this situation on board level.
Question
1) I want to receive encoded data using UART, not HDAT0,1, then do I need 4
UART?
2) If I receive it as UART, Can I use interrupt or DMA to receive data? I
don't know the mechanism of UART reception.
Using interrupts and DMA depends on your MCU. But you need those 4 different UARTs and they need to be real hardware UARTs. If each VS1063 has own crystal, they will operate slightly different speed even if the UART speed is same. You will also receive samples at different time so somewhere has to be some kind of syncing or maybe not if you send them to another VLSI chip where you can fine tune the samplerate.

To overcome this asynchronous data input make one chip as master with 12.288MHz crystal, enable I2S MCLK output and route I2S_MCLK to other VS1063 XTALI pin so that all chips run in sync. Some buffering and maybe small series resistor to dampen reflections may needed to get a good clock for the chips.

And now we have another problem. In worst case UART reception happens exactly same moment and interrupts are triggered in all 4 UARTs at same time and this is software problem which requires some clever coding if your interrupt controller is too dumb. But this depends on the MCU.

On the other hand if you read through SPI, you may have enough time to read all four chips before first one needs to be read again but this needs to be checked.

Anyway interesting problem and I'm looking forward to hear how you handle the timing constrains.
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pasi
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Re: multiple encoding with vs1063a

Post by pasi »

Hannu wrote: Wed 2021-04-21 9:42To overcome this asynchronous data input make one chip as master with 12.288MHz crystal, enable I2S MCLK output and route I2S_MCLK to other VS1063 XTALI pin so that all chips run in sync.
Other options are to buffer the XTALO of one vs1063a and feed that to the XTALI of the others (and leave their XTALOs unconnected), or run them all from an oscillator (but then you may want an oscillator that has a powerdown mode).
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EMBED_LU
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Re: multiple encoding with vs1063a

Post by EMBED_LU »

Thank you for answer.
I have one more thing to ask.
Do I need each DREQ pin, total 4?
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pasi
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Re: multiple encoding with vs1063a

Post by pasi »

The safest would be to have separate DREQ connected for each vs1063a. Otherwise you would need to depend on delays (e.g. after reset) and/or try to read the DREQ state through the serial control interface (SCI).
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