Designing my PCB.. Have some questions

Discussion about writing software for VS1005 and the VSOS Operating System. Also posts about VS1005-related hardware design and device drivers should be posted here.
msat
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Designing my PCB.. Have some questions

Post by msat »

Hello!

I am happy to say that my project is moving forwards in a sensible direction after taking too many detours, and am in the process of designing my PCB. I'm basing the foundation on the VS1005 Breakout Board v2.1 schematic, and have some questions regarding things I can omit:

First off, I will not be implementing an RTC or FM receiver, so do I still need to power and decouple pins 64 & 74 as seen in the BOB schematic?

In the VS1005 datasheet it says "Connect FVDD (pin 6) to IOVDD (pin 7). This is a work-around for a VS1005G boot timing criticality that causes boot problems in early VS1005G production lots." This is also reflected in the latest BOB schematic. Is this still necessary/recommended?

Additionally, I would like to power a preamp stage from the AVDD regulator. Should be less than 2mA draw. This is acceptable, correct? Note: I will not be using the headphone drivers, so I assume I should have plenty of overhead.

My device will have two user buttons. I want either of them to be able to act as the power button, but I also need to be able to know which one is being pressed. Of course I could try to go with DPST switches where one circuit from each switch drives the PWRBTN input, and then separate circuits from the other half of the switches going to their own IO pins supplied by IOVDD (such as per the developer board schematic). I'd prefer to use SPST switches to feed both PWRBTN and their appropriate IO pin. I assume a resistor divider can be used from VHIGH to an IO pin similar to what is done with PWRBTN when the chip is powered up and running, but is it safe to feed any power to the GPIO in that time before the chip powers up?

Thanks!
Hannu
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Re: Designing my PCB.. Have some questions

Post by Hannu »

Hi!

Good questions.
RTCVDD... I would route this just to CVDD or leave floating if no RTC crystal is installed. But at least the wrong solution is to ground it. If you power it, then for sure the RTC memory is powered. It is used at least hiresrecorder.

RFAVDD is safe to disconnect.

FVDD: R21 0hm and not assembled. So no need to connect, but CF1 cap is needed.

AVDD: Probably OK. The regulator can give you that current. Some one transistor amplifier in A-class and good amount of decoupling capacitors keep the AVDD clean and doesn't get you into trouble. The no part is that even there is some amount PSNR, it is possible get so much noise to the rail that it is audible from ADC or DAC.

I attached some idea about the buttons. Calculate the driver so that there is something like 3V.
Attachments
my_first_thought.png
my_first_thought.png (12.52 KiB) Viewed 447 times
msat
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Re: Designing my PCB.. Have some questions

Post by msat »

Thank you for the quick response, Hannu!

I will do as you say regarding the regulators/power inputs. I will also keep an eye on AVDD and attempt to keep the rail noise-free.

Thanks for the schematic! When you say "Calculate the driver so that there is something like 3V." do you mean to calculate the the divider network so that there is 3V at the GPIO pins? So it is safe to have voltage (at high impedance) at GPIO pins before the chip is even powered up?
Hannu
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Re: Designing my PCB.. Have some questions

Post by Hannu »

That schematic was about how to do a OR port with diodes and have a level shifter. I din't thought about the peculiarities of power button. One thing I missed in that circuit, is a capacitor for power button and bleed resistor for it so it won't start the chip too easily because diodes can't pull it down to zero. It would also catch some spikes through R1D1 and R2D2 network and give small protection. Also in software you'll have to filter out the switching or add also capacitors to GPIO lines.

If voltage divider is done for example with 22k and 33k resistors, then 100-470 k bleed resistor could be good. This is the easy place to do BOM optimization. values aren't critical. I would just throw some commonly used components, do the resistor math and check how slow the RC would be.

And have a look at datasheet how the PWM works. PWRBTN also controls it. If you are using it for example display backlight dimming.

When pin rises above IOVDD the protection diode starts to conduct IOVDD. It could partially power the chip. However if the impedance is high enough, there isn't current enough, voltage drops to somewhere around 0.3-0.6 on the pin and also the reset circuitry (internal and external) should keep the chip in reset if it even tries to do something.

The situation is exactly same what is happening on the UART. If you power off the chip and UART cable is connected, RX pin would have 3.3V from the UART cable.
msat
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Re: Designing my PCB.. Have some questions

Post by msat »

Thank you for the information, Hannu.

I will add a capacitor and bleed resistor among other things to the PWRBTN circuit to make it more similar to the developer board.

I figured GPIO protection diodes might get forward biased and start conducting in such a situation, but I didn't think it would cause any issues, at least with low current through them. You have confirmed my suspicions.

Thanks again!
msat
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Re: Designing my PCB.. Have some questions

Post by msat »

I'm back with some fresh new questions!

The BOB and Dev Board have similar line-in circuits, so I want to know what the significance of some of the components are.

First, there is the 100k resistor to ground. The VS1005 datasheet states an input impedance of 100k for the mic/line inputs. Does this resistor set that impedance, or is the total input impedance in this case actually 50k (100k input impedance in parallel with 100k resistor)? What are my options here? I will be driving the ADC input with an op-amp circuit.

Then there is what appears to be a low-pass filter consisting of a series 100 Ohm resistor and a 10nF shunt capacitor. This sets a corner frequency of ~159kHz. Why this frequency? Can I change these values? I actually need to incorporate a low-pass filter with a ~6kHz corner frequency anyways.

Thanks!
Hannu
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Re: Designing my PCB.. Have some questions

Post by Hannu »

It is normal signal conditioning so that the in-band signal is good. and out-of-band signal is rejected. The 159 kHz is probably been good enough so that there isn't too much phase delay and AD can be used in 96 kHz mode.

Have a look at: viewtopic.php?f=9&t=69

Most of the time you can think opamp as 0 ohm output, infinite input impedance and remember that + and - are in same voltage. Texas Instrument has a good reference guide https://www.ti.com/amplifier-circuit/an ... guide.html Most of the time it is enough to solve at least my analog problems.

I draw again something quickly. The R3 and C3 are high frequency suppressor. I would leave that as is or increase both values to next value so the filter comes down a bit. I could maybe go down to somewhere around 50-100 kHz. But the I would need to start thinking the quality of the components. For example some capacitor can be capacitor in 100 kHz, but higher value capacitor from same series can be resistor and capacitor. However this is more common when designing switch mode power supplies.

The C2 value is limiting on the lower frequencies and makes DC block. Check that it is big enough that your low frequencies pass through it. R1,R2 and C1 creates the real low pass and is your gain. If you are interested in phase, design it to 10k and if you are interested in filtering just frequency, filter lower, add stages and make filter steeper.

Then in VS1005 run ADC in 48kHz, load FTIDCBL library which removes digital DC, and take Octave and DSP library viewtopic.php?f=7&t=1593 and design difgital filter, add your own processing to the chain and do whatever with the signal.
Attachments
A quick design of an opamp input
A quick design of an opamp input
AD_and_amp.png (11.51 KiB) Viewed 382 times
msat
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Re: Designing my PCB.. Have some questions

Post by msat »

Once again, your responses are greatly appreciated, Hannu.

I believe I have found some errors in my thinking. I won't concern myself with the 159 kHz filter and I will leave it as-is for now.

I was trying to accomplish all my needs with a single IC dual op-amp (1/2 for preamp, 1/2 for bias voltage buffer). Instead I may need to use 2 ICs, with the second one used to implement multi-order low-pass filters for anti-aliasing.

I have come across the thread on the FIR filters before and have considered the software approach to low-pass filtering. Power efficiency is of high importance for this project so I will need to find out if there is a worthwhile benefit to the hardware approach - I had only been assuming there was. My intention was to sample a mono channel up to 24kHz and encode it to mp3 at the recommended bit rate.
msat
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Re: Designing my PCB.. Have some questions

Post by msat »

I have some new questions, but they are still relevant to this thread, so I will ask them here:

I need to implement USB Dedicated Charging Port (DCP) detection, as outlined in the USB battery charging specification. I don't want to increase my BOM unnecessarily, especially if there is the possibility to implement it with the 1005's built-in USB hardware. I think I can accomplish it if I can do the following things, which the datasheet didn't seem to specify:

I would need to simultaneously be able to enable "fs_rpu_ena" (as it is called in "Figure 23: VS1005g UTM functional block diagram" of the datasheet) - the D+ pull-up resistor, as well as "host_rpd_ena" - the 15k D+/D- pull-down resistors. I would also need to read the states of the "usbp_bit" & "usbn_bits".

Can control of fs_rpu_ena and host_rpd_ena be accessed directly from user code at some address? What about the usbp_bit & usbn_bit?

Thanks,
Mark
Hannu
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Re: Designing my PCB.. Have some questions

Post by Hannu »

I am also on uncharted waters and I'll try to get you a better answer, but USB_UTMIW register is the one register to poke.

I took a look at the spec and then I remembered again that this is USB. Too many TLAs and ETLAs for my taste to give quick answer.

So you want USBP 1.5k pull-up and USBN 15k pull-down. Is there need for some signaling ? Or just to keep the system passive and resistors on?

I found this from kernel sources (scsi.c) and optimized it for you :)

Code: Select all

u_int16 MyUSBReadLines(void) {
   return PERIP(USB_UTMIR)>>14;
}
/* Actually fastest implementation: #define MyUSBReadLines() (PERIP(USB_UTMIR)>>14) */

What else is needed, I don't currently know. Some hints could be found from UsbHost porgram code and umsc code from kernel If you want to have an interesting journey around USB hardware.
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