VS1053 low audio level

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arlaor
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Posts: 7
Joined: Tue 2019-04-23 21:54

Re: VS1053 low audio level

Post by arlaor »

Thanks for you reply @Panu i go it

I have observed in the different breackout board,
http://www.vlsi.fi/fileadmin/evaluation ... SP_sch.pdf
http://www.vlsi.fi/fileadmin/evaluation ... yer_07.pdf
http://www.vlsi.fi/fileadmin/evaluation ... ematic.pdf
and this http://www.vlsi.fi/fileadmin/evaluation ... xxpp17.pdf, connected to 2.8 volts
different combinations of filters for the RIGHT LEFT and GBUF outputs and I would like to know which one delivers the best sound quality both connected to headphones and connected to an audio receiver (example marants receiver)
Or what does it depend on to apply each of these filter systems?
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Panu
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VS10xx analog output and declick circuit

Post by Panu »

Yes, different designers have improved their visions over the years. The analog output is nearly the same in each of our ICs, but the ratings for AVDD have changed between different IC's. (CVDD is even more different in each IC.)

For VS1053, find the VS1053 Hi-Fi Player schematic, that's very good for the VS1053 headphone out. For VS1005, find the VS1005 Hi-Res Player schematic, that's the best one and the analog is also suitable for the VS1053. The VS1010 Handbook has the best explanation for headphone out and line out, but that's only available in print. Basically follow the instructions in the Line Out diagram, of which the link is below, and combine all information from all these sources. The most important things are 1) combined ground plane (single ground plane for analog and digital), 2) no digital signals crossing analog signals in ANY layer, 3) RCAP capacitor needs to be without via's and 4) line out to external equipment needs proper filter. We have also nearly perfected a de-click circuit for the line out, which very nearly eliminates the power-up pop (click) sound from the line out.
left_right_gbuf_rcap_stabilizer.png
left_right_gbuf_rcap_stabilizer.png (13.92 KiB) Viewed 4348 times
Normal RCAP reference capacitor, LEFT+RIGHT+CBUF(GBUF) stabilizer RC circuits, use for all VS10xx devices.
 
For Line Out, this is the best circuit, I think, so far:
declick_1.png
declick_1.png (44.52 KiB) Viewed 4348 times
Line Out declick circuit using NPN. DE_CLICK must be a GPIO signal (from VS chip or microcontroller) which is floating or high at boot time and can be programmed to be output low after VS10xx analog has been started. This way the Line Out rises smoothly from ground to GBUF/CBUF/RCAP voltage after VS chip analog startup.

-Panu
SJS
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Re: VS1053 low audio level

Post by SJS »

Hi Panu,

i have realized your declick circuit with the transistors above but still get a big "plop" when unmuting. In my circuit there is a small difference, i did not populate the 560R resistors R37/R39.

Do you think this is the problem i observe? Or is this maybe related to the class D amp behind (with capacitors to ground at the negative inputs and with capacitors on the positive input coming from VS1053B)? The amp itself does not produce click/pop noise on starting, only when the running amp gets the unmuted input from the VS1053.

Thanks,
Stefan
Hannu
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Re: VS1053 low audio level

Post by Hannu »

First of all, I'm not really familiar with VS10xx chips.
I can't say straight what might be problem but I can give some debugging hints

In SCI_STATUS register there are bits 3 and 2. setting and resetting them will give you DAC enable and disable transitions. And I presume that you have easy control on the declick signal.

You can try to different delays for driving the declick or even ramp it with PWM.

Another thing is that you could try to drive ramp from DAC so the signal is low, declick is released and ramp rises to zero point.

The 10u capacitor and left R41 controls the delay.

If you have access to oscilloscope, poke with it C22 AC coupling capacitor from both sides and post some pics if the behaviour isn't obviously wrong and easy to fix.
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pasi
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Re: VS1053 low audio level

Post by pasi »

I have fiddled with a similar declick circuit as in Panu's post in another project.

The function is:
- The declick signal is input (not driving) at reset, so when power is applied, the pull-up drives the "mute" transistor to pull the analog output to ground.
- The declick IO pin is then set high and to output mode, continuing the "mute".
- The DAC analog outputs are then allowed to bias, with DAC powerdown off and DAC drivers enabled. Enabling the DAC drivers as soon as possible from SCI_STATUS might reduce the time you need to wait.
- The declick IO is then brought low to stop the "mute" transistor from pulling the output low. Preferably the declick IO is brought low with PWM within a few seconds (the lower frequencies the amp and speaker can reproduce, the longer). The 10uF capacitor C2 is intended to smooth out the PWM, but in reality, the value 10uF seems much to small for regular PWM. The base frequency of the PWM comes through and you get a low-level low-frequency "frrr" from the bass element. And for a straight high-to-low (or low-to-high for shut-down) transition of the declick signal, 10uF is completely insufficient if you also want to pass low frequencies through the DC block.

For "this other thing", I created a version of impulse density modulation / sigma-delta modulation using a pseudo-random sequence together with the pulse width ratio control parameter. This removes the base frequency, replacing it with higher-frequency noise, which is much easier on the ear. With this and high enough frequency (the VSDSP code for it is just 4 cycles per iteration thanks to the GPIO bit engine), a 100uF capacitor would probably be sufficient.

So, try driving the IO pin with PWM from high to low and check if that's acceptable.

It might also help debugging if you perform the steps very slowly and note what exactly is the source of the snap.
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SJS
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Re: VS1053 low audio level

Post by SJS »

Thanks a lot @Hannu and @pasi for your suggestions!

The signal at the transistor is exactly what you described: high via pull-up at power on, then continued by a GPIO of the VS1053 (first data direction register is set to output und GPIO is set to be high) and then after ~1000ms the GPIO of the VS1053 is set to low to unmute the circuit. That works (regarding the functionality) absolutely perfect.

At first i thought that there would be a problem while powering because there is a small "problem" with this circuit: the capacitor C22 is charged over the 1k and 10k with IOVCC, so at the very first moment the circuit is still unmuted. So the voltage at C22 rises and the muting will start after U(BE) of the transistor has reached U(BE) of ~0,7V. So first after that the muting works until it is unmuted. So an increasing C22 too much would be not a good idea because this time would be longer.

But this is not the problem here. The "plopp" comes with unmuting, so to apply PWM or an extended other hardware delay would be maybe a solution. PWM is here not easy possible because the GPIOs of the VS1053 are more for static use i think.

I will have another look on the SCI_Status register. Maybe this is software related - at the moment, first volume and tone settings are applied, then i will unmute and after that the stream is started (application is an internet radio).

But i still do not understand what the two capacitors on the negative inputs of the class d will do and if they are the origin of my problem too.

BTW: I am impressed about the sound quality of the VS1053. My design (4 Layer, all the hints from you applied regarding ground planes etc) matches very very good for the first pcb revision. I have no hearable noise, this is very impressive for an analog circuit.

Thanks for your help!
Stefan

Here are some pictures (without the class d, this module is stacked on top):
P1050554 (Large).JPG
P1050554 (Large).JPG (411.96 KiB) Viewed 611 times
P1050550 (Large).JPG
P1050550 (Large).JPG (359.87 KiB) Viewed 611 times
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pasi
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Re: VS1053 low audio level

Post by pasi »

You could upload a short vs1053b program to perform the GPIO declick PWM. vs1053b GPIO doesn't have the "bit engine" though (or even bit mask registers to set or clear GPIO pins), so my "turbo" routine cannot be used. But I quickly made a version that doesn't use those features.

You can adjust the data in the plugin file to change which GPIOs become outputs and are driven, and also the direction of drive. This code overrides the DDR register though. Other GPIOs will be turned into inputs. The precompiled version uses all 8 GPIOs that are available (depends on NEWMODE), and fades from 0 to 1 in about 4.5 seconds with 4.5x clock. You can adjust the clock or the fade speed from the plugin for shorter or longer fade.

Note: Interrupts, including DAC interrupt are not serviced during the operation. This probably isn't an issue for you, but the automatic analog driver enable countdown also isn't progressing, so you may want to wait that the drivers are enabled (SCI_STATUS) or enable them yourself before starting this. DREQ stays low until the fade is finished.

As code:

Code: Select all

#define ASM
#define STANDALONE
#include "vs1053b/hardware.h"

	.sect code,DeClickIO
	.org 0x50
	.import _applAddr
	and a0,null,a0	; ldx (i6)+1,null
	stx c0,(i6)+1	; sty c1,(i6)
	stx lr0,(i6)	; sty d0,(i6)
	ldc _applAddr,i7
	STX a0,(i7)
	//ldc 0x04,d0 //GPIO2
	ldc 0xff,d0 //all GPIOs driven
	ldc GPIO_DDR,i7
	stx d0,(i7)

$0:	ldc 16,c1 //speed (and direction, -16 to fade 1->0)
	call _DeClickIO
	ldc 0,c0 //start, 0x7fff to fade 1->0

	ldx (i6)-1,lr0	; ldy (i6),d0
	jr
	ldx (i6)-1,c0	; ldy (i6),c1

	.export _DeClickIO
_DeClickIO:
	ldx (i6)+1,null
	stx a0,(i6)+1	; sty a1,(i6)
	stx lc,(i6)+1	; sty ls,(i6)
	stx le,(i6)+1	; sty b0,(i6)
	xor d0,ones,d0	; stx b1,(i6)	; sty d1,(i6)
	ldc GPIO_ODATA,i5
	or a0,ones,a0	; ldx (i5),d1	//old ODATA //a0=fixed seed
	and d1,d0,d1	//masked out the PWM bit(s)
	xor d0,ones,d0
	ldc 16217,b1
	ldc 9043,b0	//0x951,b0
$0:	ldc 0x3fff,ls
	loop ls,$10-1
	mulss a0,b1

$11:	add b,p,a	// x(n+1) = (a*x(n)+c) mod m
	lsr a0,a1	// output: 0..0x7fff
	add a1,c0,a1	// Add the PWM ratio
	mulss a0,b1	; sty a1,(i5) //GPIO0_BIT_ENG0 bit 15 to GPIO0_8
	jnc $12
	mv d1,a0
	or a0,d0,a0
$12:
	stx a0,(i5)
$10:
	add c0,c1,c0
	ldc 0x3fff,lc	//ls and le already correct
	jnc $11
	add c1,null,c1

	nop
	jns $1	
	nop
	or d1,d0,d1
$1:	stx d1,(i5)	//leave it in the desired state
	ldx (i6)-1,b1	; ldy (i6),d1
	ldx (i6)-1,le	; ldy (i6),b0
	ldx (i6)-1,lc	; ldy (i6),ls
	jr
	ldx (i6)-1,a0	; ldy (i6),a1

	.end
As plugin:

Code: Select all

#ifndef SKIP_PLUGIN_VARNAME
const unsigned short plugin[] = { /* Compressed plugin */
#endif
	0x0007,0x0001, /*copy 1*/
	0x8050,
	0x0006,0x0064, /*copy 100*/
	0xb080,0x184c,0x3e11,0x3805,0x3e02,0x3806,0x0007,0x9257,
	0x3f00,0x0024,
#if 1
	0x0000,0x3fc6,	//All GPIO0..7
	//0x0000,0x2006,	//GPIO7
	//0x0000,0x1006,	//GPIO6
	//0x0000,0x0806,	//GPIO5
	//0x0000,0x0406,	//GPIO4
	//0x0000,0x0206,	//GPIO3
	//0x0000,0x0106,	//GPIO2
	//0x0000,0x0086,	//GPIO1
	//0x0000,0x0046,	//GPIO0
#endif
	0x0030,0x05d7,0x3f01,0x8024,
#if 1
	0x0000,0x0405,	//Speed/direction 0x10 for 0->1 transition (in bits 6...21)
#else
	0x0fff,0xfc05,	//Speed/direction -0x10 for 1->0 transition
#endif
	0x2900,0x1780,
#if 1
	0x0000,0x0004,	//Start 0 for 0->1 transition
#else
	0x001f,0xffc4,	//Start 0x7fff for 1->transition
#endif
	0x36f2,0x1806,
	0x2000,0x0000,0x36f1,0x1805,0x3613,0x0024,0x3e10,0x3801,
	0x3e13,0x780e,0x3e13,0xf802,0xd69d,0xe3e7,0x0030,0x0655,
	0xc090,0x1407,0xb76e,0x0024,0xd69c,0x0024,0x000f,0xd643,
	0x0008,0xd4c2,0x000f,0xffce,0x2400,0x1cce,0xfe30,0x0024,
	0x4db2,0x0024,0xf202,0x0024,0x4142,0x0024,0xfe30,0xb401,
	0x2800,0x1cd4,0xf400,0x41c0,0xc060,0x0024,0x3d00,0x0024,
	0x4458,0x0024,0x000f,0xffcd,0x2800,0x1b14,0x458a,0x0024,
	0x0000,0x0024,0x2800,0x1f04,0x0000,0x0024,0xc76e,0x0024,
	0x3d01,0xc024,0x36f0,0xd807,0x36f3,0xd802,0x36f3,0x580e,
	0x2000,0x0000,0x36f0,0x1801,
	0x000a,0x0001, /*copy 1*/
	0x0050,
#define PLUGIN_SIZE 108
#ifndef SKIP_PLUGIN_VARNAME
};
#endif

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SJS
Senior User
Posts: 22
Joined: Mon 2021-01-25 19:20

Re: VS1053 low audio level

Post by SJS »

Big thanks @pasi for your effort!

I will try to get that into my code - but to be honest, i am good in hardware but worse in software :-)

For me, a hardware solution seems to be easier and eliminates the origin of the problem. At the end a software PWM does that, what the actual hardware circuit is not able to realize on his own. The RC constant of the 10k/10µ seems to be much too low to get slow ramp. With starting unmuting and discharging the 10µF, the muting is 100% active until U(BE)~0.7V is reached, a few millivolts below are then enough to unmute completely because of the hfe of the transistor. So the unmuting ramp is only a few ms or µs long. The problem here is that the transistors are current controlled and not voltage controlled.

Increasing that RC constant has the undesired side effect that at power on, the activation of the mute is delayed too (because the 10µ has to be initially charged by the 10k pull-up to IOVCC).

I will post a modified circuit later.
SJS
Senior User
Posts: 22
Joined: Mon 2021-01-25 19:20

Re: VS1053 low audio level

Post by SJS »

So here is a modified circuit which should solve the problem - now there are two independent time constants for powering up and for unmuting:
snip_20220418195126.png
snip_20220418195126.png (21.18 KiB) Viewed 540 times
Signal VS1053_mute:
Controlled by µC or GPIO of the VS1053B as before (you can use GPIO2...GPIO7 for that, GPIO0/GPIO1 are reserved for MIDI modus and should be pulled down for streaming applications). This signal is pulled low at start by the 47k pull-down resistor. To unmute, set this signal to high.
If a GPIO of the VS1053 is used, all GPIOs of the VS1053 are input at power-up so this will be safe. Declare the pin as output and pull low to continue the muting status - later if you want to unmute, simple set this pin to high level.

Power-on:
The two mosfets are now immediately on when power is applied (1k/10µ = 10ms time constant of R60/C53) and the circuit is muted. R60 can be reduced for lower time constant, but this combination should be sufficient because the rising of VCC takes some time too.

Unmuting:
When the signal VS1053_mute goes high, the time constant of R59/C53 will be applied. The voltage at C53 drops down (4.7s time constant) and because the gate input of the mosfets are voltage controlled, a much more wider linear area of unmuting is used (=slow ramp up of the output signal).
For a shorter or a longer ramping from muting status to full volume level simple adjust R59 (lower = shorter ramp, higher = longer ramp).

Muting while in action:
Simple set the signal VS1053_mute (from a µC or an GPIO of the VS1053) to low, the output is muted immediately without hearable ramping.

I will integrate that in my next pcb revision and give you feedback.
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